Memory plays an essential role in the design of electronic systems where storage of data is required. In this paper comparative analysis of different DRAM (Dynamic Random Access Memory) cell based memory array structure has been carried out in nanometer scale memories. Modern advanced processor use DRAM cells for chip and program memory. But the major drawback of DRAM is the power dissipation. The major contribution of power dissipation in DRAM is off-state leakage current. Also the improvement of power efficiency is difficult in DRAM cells. This paper investigates the power dissipation analysis in DRAM cells. Here 1T1C dram cell, 3T dram cell, 4T dram cell has been designed using TANNER EDA Tool.
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