We present a Hoare-style specification and verification approach for invariants in sequential OO programs. It allows invariants over non-hierarchical object structures, in which update patterns that span several objects and methods occur frequently. This gives rise to invalidating and subsequent re-establishing of invariants in a way that compromises standard data induction, which assumes invariants hold when a method is called. We provide specification constructs (inc and coop) that identify objects and methods involved in such patterns, allowing a refined form of data induction. The approach now handles practical designs, as illustrated by a specification of the Observer Pattern.
An algebraic specification is viewed as a black box that rewrites input to a ``most basic'' canonical form. We argue that a canonical form should be given for each specific specification, to prevent ``cheating'' in the implementation. Furthermore, we argue that the definition of the canonical form may sometimes require semantic rather than syntactic information.To relate an OO implementation to a specification requires opening the black box to some extent; we assess the choices to be made here.
The use of object-based programming techniques h.elps to reduce the cost of software development and maindenance, due to the benefits of reuse, information h.idin.g and encapsulation. This is especially helpful in complex, real-time systems that are highly parallel a,nd distributed, due to thear magnitude. The paper presents a semi-preemption execution. model of objectbased real-time systems th,at simplifies reasoning about th.e quality of particular-process-to-processor assignments. Th,e m,odel is used t o define system properties such. as in,ter-process parallelism, processor utilization and inter-processor communication. Additionally, we present an innovative assignment algorithm that incorporates feasibility constraints, and is guided b y an objective th.at balances minimum communication agnin.st maxim.um. parallelism. This work is part of a complete nssignin.ent an.d pre-run-tim.e scheduling approach for distributed real-time systems. IiitroductionDuring the last decade, dependability of computer systems has become ail increasingly important topic. In addition t,o correct functionality, dependability includes tim.eliness, i.e., real-time constraints imposed on t,he t,asks of the system must be satisfied. A condit,ion often required to guarantee timeliness is that applicat,ions and the environment have to be fully, or almost fully, predict>able. Otherwise, due to the overhead of scheduling a transient burst of new tasks at run-time, it might become impossible to satisfy the HRT constraints of cert,ain tasks. For instance, simu1a.tion results of an evduation of the run-time scheduling strategy described in [7] show that timeliness cannot be guaranteed in all circumstances. Given such a model, schedulability analysis techniques can be used t,o analyze an application [lo]. However, we prefer to schedule a, hard real-time system pre-run-time, such that. all t,iming constraint,s are satisfied and consistency of all resources, including processors, communication media and devices, is guaranteed [12]; with this approach, the run-time system simply dispatches and executes tasks according to the schedule constructed pre-run-time.We consider a distributed memory MIMD system that consists of a set of homogeneous processors P R , connected by a set of communication media CM. A communication medium is either a bus that connects a set of usually more than two processors or a link that connects two processors directly. The only assumption made about the interconnection configuration is that there is a set routes consisting of links, busses and processors between each pair of different processors. Each route is a sequence of triples sprj E PR, cmj E C M , rpri E PR, that indicates via which processors, busses and links, a communication from processor sprl to rprr has to be routed. Additionally, the system contains several shared memory modules and a set of physical devices DV, of different types such as sensor, actuator, and disk. Each device is assigned and physically connected to a particular processor after assignment of ...
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