The use of authentic real-world problems that reflect the applied nature of mathematics is not prevalent in formal secondary school settings. In this study, we explore the interface between workplace mathematics, particularly tech-related real-world (TRW) problems, and school mathematics, through the explication of mathematical modeling. The research questions are (1) in which tech domains can real-world problems be identified that can be addressed using mathematical modeling for the secondary school level? (2) Which methods do engineers use to simplify tech-related problems for non-experts in their field? (3) In which areas in the secondary mathematics curriculum can TRW problems be mapped? We present a three-phase model which yielded the creation of a pool of 169 TRW problems. The first two phases of the model included extracting authentic problems from the work of tech engineers and simplifying them to be meaningful or perceivable to students. These were explored by conducting task-oriented interviews with senior tech engineers and scientists from leading companies and universities. The third phase was accomplished by interviewing mathematics education experts, and included verifying the compatibility of the problems with the formal, secondary-level mathematics curriculum. The study has methodological, theoretical, and practical contributions. These include methodology that enables identifying TRW problems that are compliant with the secondary mathematics curriculum; adding to the literature about mathematical modeling by demonstrating the interface between workplace mathematics and school mathematics; and creating a large pool of TRW problems that can be used in secondary school math lessons.
We introduce the Micro-Operation Cache (Uop Cache -UC) designed to reduce processor's frontend power and energy consumption without performance degradation. The UC caches basic blocks of instructions -pre-decoded into micro-operations (uops). The UC fetches a single basic-block worth of uops per cycle. Fetching complete pre-decoded basic-blocks eliminates the need to repeatedly decode variable length instructions and simplifies the process of predicting, fetching, rotating and aligning fetched instructions. The UC design enables even a small structure to be quite effective. Results: a moderate-sized UC eliminates about 75% instruction decodes across a broad range of benchmarks and over 90% in multimedia applications and high-power tests. For existing Intel P6 family processors, the eliminated work may save about 10% of the full-chip power consumption with no performance degradation.
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