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We present several optical interconnection structures which support communication requirements unique to multiprocessor systems, namely, broadcasting, multicasting, simulcasting, and multiport memory access. The structures are based on guided wave time division multiplexed channels and use coincident pulse techniques to optically demultiplex individual bits at selected destinations. We describe 1-and 2-D structures which are appropriate for processor to processor interconnections and for processor to memory interconnections, respectively.

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This paper presents a partitioned optical passive star (POPS) interconnection topology and a control methodology that, together, provide the high throughput and low latency required for tightly coupled multiprocessor interconnection applications. The POPS topology has constant and symmetric optical coupler fanout and only one coupler between any two nodes of the network. Distributed control is based on the state sequence routing paradigm which multiplexes the network between a small set of control states and defines control operations to be transformations of those states. These networks have highly scalable characteristics for optical power budget, resource count, and message latency. Optical power is uniformly distributed and the size of the system is not directly limited by the power budget. Resource complexity grows as O ( n ) for tbe couplers, O ( n J n ) for transceivers, and O [ J tl log ( n ) ] for control. We present analysis and simulation studies which demonstrate the ability of a POPS network to support large scale parallel processing (1024 nodes) using current device and coupler technology.

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Modern computer buses are typically organized by the three functions of data transfer, addressing, and arbitrationlcontrol. In this paper we present a jiber-based bus design which provides optical solutions for each of these functions. The design includes an all-optical addressing system, based on coincident pulse addressing, which eliminates the latency contribution and bandwidth limitation associated with electronic address decoding. The control system uses rime-of-flight relationships between a priority chain and a feedback waveguide to implement fully distributed asynchronous and self timed bus arbitration.

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