The nonlinear Fourier transform (NFT) based signal processing has attracted considerable attention as a promising tool for fibre nonlinearity mitigation in optical transmission. However, the mathematical complexity of NFT algorithms and the noticeable distinction of the latter from the "conventional" (Fourier-based) methods make it difficult to adapt this approach for practical applications. In our work, we demonstrate a hardware implementation of the fast direct NFT operation: it is used to map the optical signal onto its nonlinear Fourier spectrum, i.e. to demodulate the data. The main component of the algorithm is the matrix-multiplier unit, implemented on field-programmable gate arrays (FPGA) and used in our study for the estimation of required hardware resources. To design the best performing implementation in limited resources, we carry out the processing accuracy analysis to estimate the optimal bit width. The fast NFT algorithm that we analyse, is based on the FFT, which leads to the O(N log 2 2 N ) method's complexity for the signal consisting of N samples. Our analysis revealed the significant demand in DSP blocks on the used board, which is caused by the complex-valued matrix operations and FFTs. Nevertheless, it seems to be possible to utilise further the parallelisation of our NFT-processing implementation for the more efficient NFT hardware realisation.
Research motivation. When developing microcontrollers, manufacturers try to include as many different types of peripherals as possible in order to increase the marketing attractiveness of their products. On the one hand, with a large assortment of various peripheral modules, it is very difficult to implement several devices of the same type in the microcontroller: manufacturers are mainly limited to 1-2 instances, in rare cases 4 modules of the same type are included. On the other hand, most software projects do not use all the peripherals of modern microcontrollers and many devices are left unused, while there may be a shortage of other types of modules. Another problem that has become especially noticeable for microcontrollers used in the field of IoT is the cryptographic protection of data that is transmitted through built-in information exchange interfaces. The main efforts of researchers and developers of cryptographic data protection methods were aimed at reducing energy-intensive operations, memory access iterations and speeding up encryption processes while maintaining a high level of cryptographic protection and enabling efficient data distribution within IoT devices networks. Research results. This paper presents an alternative approach to the manufacture of peripheral modules as part of microcontrollers. The authors propose to use a configurable software processor module based on the MIPS architecture with a reduced instruction set and limited capabilities. Conclusions. This approach would make it possible to dynamically change the functionality of peripheral modules in accordance with the requirements of the developed software solution, which in turn will increase the efficiency of the microcontroller chips capabilities utilization. In addition, the transfer of data stream encryption functions to the reconfigurable core of the peripheral module will provide fast and transparent cryptographic protection, as well as allow offloading the microcontroller core and increasing the energy efficiency of chips while reducing their production cost.
The object of research is the adaptive switching weighted median image filter (ASWM) algorithm. This algorithm is one of the most effective in the field of impulse noise suppression. The computational complexity and algorithmic features of this adaptive nonlinear filter make it impossible to implement a filter that works in real time on modern PLD microcircuits. The most problematic areas of the algorithm are the weight coefficient estimation cycle, which has no limit on the number of iterations and contains a large number of division operations. This does not allow implementing the filter on PLDs with a sufficiently effective method. In the course of the research, the programming model of the filter in Python was used. The performance of the algorithm was assessed using the Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) metrics. Modeling made it possible to find out empirically the number of iterations of the cycle for estimating the weight coefficients at different levels of noise density and to estimate the effect of artificial limitation of the maximum number of iterations on the filter performance. Regardless of the intensity of the noise impact, the algorithm performs less than 40 iterations of the evaluation cycle. Let’s also simulate the operation of the algorithm with different variants of the division module implementation. The paper considers the main of them and offers the most optimal in terms of the ratio of accuracy/hardware costs for implementation. Thus, a modified algorithm was proposed that does not have these disadvantages. Thanks to modifications of the algorithm, it is possible to implement a pipelined ASWM image filter on modern PLDs. The filter is synthesized for the main families of Intel PLDs. The implementation, which is not inferior in terms of SSIM and PSNR metrics to the original algorithm, requires less than 65,000 FPGA logical cells and allows filtering of monochrome images with FullHD resolution at 48 frames/s at a clock frequency of 100 MHz.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.