This paper presents the analysis and software implementation of a robust synchronizing circuit, i.e., phase-locked loop (PLL) circuit, designed for use in the controller of active power line conditioners. The basic problem consists of designing a PLL circuit that can track accurately and continuously the positive-sequence component at the fundamental frequency and its phase angle even when the system voltage of the bus, to which the active power line conditioner is connected, is distorted and/or unbalanced. The fundamentals of the PLL circuit are discussed. It is shown that the PLL can fail in tracking the system voltage during startup under some adverse conditions. Moreover, it is shown that oscillations caused by the presence of subharmonics can be very critical and can pull the stable point of operation synchronized to that subharmonic frequency. Oscillations at the reference input are also discussed, and the solution of this problem is presented. Finally, experimental and simulation results are shown and compared.
This paper presents the analysis and software implementation of a robust synchronizing circuit -PLL circuitdesigned for using in the controller of active power line conditioners. The basic problem consists in designing a PLL circuit that can track accurately and continuously the positivesequence component at the fundamental frequency and its phase angle, even when the system voltage of the bus, to which the active power line conditioner is connected, is distorted and/or unbalanced. The fundaments of the PLL circuit are discussed. It is shown that the PLL can fail in tracking the system voltage during the startup, under some adverse conditions. Moreover, it is shown that oscillations caused by the presence of sub-harmonics can be very critical and can pull the stable point of operation synchronized to that subharmonic frequency. Oscillations at the reference input are also discussed, and the solution of this problem is presented. Finally, experimental and simulation results are shown and compared. controlled oscillator vco output u*(t) Fig. I Block diagram of basic PLL structurezation between time-varying signals is the use of a phaselocked-loop (PLL) system 0 that can be described by the basic structure shown in block diagram form in Fig. 1. This simplified PLL structure comprises a phase detector (PD). a loop filter (LF) and a controlled oscillator (VCO), each of which can be implemented in several different forms. If the signal to be tracked (reference input) is an analog signal, then the most suitable type of PD to be used is the product-type one. The use of a product-type PD plus a linear LF causes the PLL to behave linearly for small variations on input, yielding a linear PLL. FUNDAMENTALS OF THE LINEAR PLL C I R C U I TIn this work, the reference input is represented by a space vector, as well as the VCO output:(1) 11, (1) = U,e""''+"') and l 1 2 ( t ) = u2e/(1121+@>' In stationary (a;R) reference frame, both signals can be written in the form u(r) = 11, + ,jirp Three-phase input signals can be easily converted to this form through the Clarke Transformation. Altematively, these signals can be represented in a synchronously rotating reference frame (through the Park Transformation) as shown in [5], with similar results.The angular frequency w2 of the VCO output signal is related to its input U,([) by:where wl, is called the centerfieqirency.The phase detector operates on the product of both space vectors ul(/) and u2 (/). For this reason it is often called a vector-prodirct phase derector (VP-PD). Its output can thus be written as ii&) = Im{i/l(/) , I /~( / ) ) , which yields:for CO, = lo2 = CO" (PLL in the locked state at the center frequency).For small phase deviations, this relationship can be approximated linearly by:where K,, = UlU2 and be(/) = @,(I) -4?(r).If the amplitudes U / and U, are both normalized to unity, then (4) further simplifies to z/,l(r) = As a result, the linearized behavior of the PLL can be described by the simplified block diagram shown in Fig. 2. In the block diagram shown in Fig. 2...
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