In the context of SOI, thermal constraint is more serious for analog devices. Besides the hot-spot effect, the temperature gradient on symmetrical devices may cause errors and even failures in the function. In order to handle these problems, this paper introduces an accurate thermal model into the placement process. Based on the geometric symmetry which is achieved with Corner Block List (CBL) for the first time, the thermal model helps to flnd the thermal-optimal placement. And the experimental results show this method is promising. I IntroductionAs the increase in frequency of the circuits and the widely use of SOI (silicon-on-insulator), thermal constraint is becoming more and more important, especially for analog devices, because these devices' operations rely greatly on the temperature. As power is dissipated in the channel of an analog device, the temperature rises due to the poor thermal conductivity of the relatively thick buried oxide layer of SOI. Then the risen temperature will affect the channel current through the carrier mobility, threshold voltage and velocity saturation mechanisms [1] and this may cause hot-spot and temperature gradient.And the thermal constraint may be even more serious for symmetrical devices, for the symmetrical devices' operations rely more on the relative parameters of their corresponding devices than those of their own. However, the traditional works [2] [3] [4] [5] on symmetry constraint assume that the circuit is isothermal since the substrate material has good thermal conductivity. Therefore, they mainly focus on the geometric symmetry by using simulated annealing (SA) with some topological representations such as SP [2], TCG-S [3], segment tree [4] as well as Binary tree [5].But this assumption must be questioned in the context of thermal-sensitive symmetrical analog devices and the use of SOI technology. The isolating buried oxide layer has a lower thermal conductivity, often over 100 times worse than silicon. As a result, even with the relatively moderate power levels encountered in typical signal path transistors, increases in the channel temperature of tens of degrees due to self-heating effect can be observed. And some of the heat generated by the distinct devices will flow laterally before reaching the substrate. Thus the devices around them will be affected, and the temperatures of these neighboring transistors will also rise. The temperature gradients resulting from self-heating and thermal coupling lead to *This work is supported by NSFC 90307005 nonisothermal conditions. This can lead to a much higher temperature on some devices and it is not consonant with the assumption for the traditional work on symmetry constraint.The hot-spot effect may cause failure on the performance of analog devices, because high temperature will reduce drawn current dramatically. And the temperature gradients of symmetrical devices may cause mismatch or even failure on the performance. Therefore, it is very necessary to propose a method to handle thermal-driven symmetry constraint in...
In the design of analog circuits, some pairs of devices are constrained to be placed symmetrically with respect to a common axis in order to cope with the device matching. In this paper, symmetry constraint is coped with CBL representation. In our algorithm, the incompleteness and redundancy of CBL can be corrected. And the experimental results show the effectiveness of our method.
Abstract-This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three observations: thinking of hierarchical design for analog, structural feature of circuit based on signal-path, requirements of matching/symmetry constraint and the reduction of parasitics. The thinking of hierarchical design makes the whole analog circuit divided into core-circuit and bias-circuit. So, the algorithm is designed as two independent steps: core-circuit is placed firstly, and then bias-circuit. The structural feature of circuit based on signal-path and the requirement of matching/symmetry constraint decide the placement pattern of core-circuit. The reduction of parasitics requires the algorithm to select the optimal variants to realize the placement. Experimental results demonstrate that this algorithm can generate the compact layout with high performance and it is universal and effective. I IntroductionNowadays, SOC integrates all of the circuits on one chip, including digital and analog parts. The physical design of digital circuits is automated to a large extent but the layout of analog circuits is still a manual, time-consuming and error-prone, which makes custom analog layout be a bottleneck in the mixed-signal design flow. The fast changes of demands in ASIC market also require analog layout automation tool to accelerate the whole design process. Thus, the time from product demands to market can be greatly shortened. Analog placement is a vital step in the design flow from circuit schematics to layout. Analog placement automation tool must not only provide a good rectangle packing functionality, but also satisfy analog specifications. Mismatch and parasitics induced by the layout are the most important factors to affect the performance of analog circuit.In the past two decades, researches have done many researches about analog placement, but no successful commercial products have existed. Generally speaking, the existing methodologies for analog placement automation can be classified into the following several categories.The constructive placement techniques, which adopts the increase placement thinking that one module is selected at a time and positioned in the best available location, which is calculated by an evaluation function or directed by an expert system. A placement tool based on expert knowledge is developed in well with the problem size, but the final placement can be poor because there are no effective methods to decide the order of modules and the view of global optimization and the costs of supporting expert system are expensive.A placement technique iteratively combining min-cut partitioning and force-directed placement (FDP) has been employed in an interactive environment for full-custom designs [2]. This method can fast obtain a feasible placement solution satisfying geometrical constraints but not ensure that the placement is a good placement.Nowadays, the simulated annealing This paper a...
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