Software Defined Radio (SDR) is the ubiquitous technology employed in Electronic Communication Systems. Widespread availability of multi-processor SoC technologies lead the way to replace the analog hardware blocks with software driven flexible heterogeneous computing blocks. One of the potential requirement of Software defined Radio/Receiver is assessment of spectrum occupancy over the specified frequency spectrum. The SDR has fast analog-to-digital converter (ADC) that digitizes the band limited RF or IF signals followed by Digital Down Converter (DDC) that optimizes the bandwidth (BW) and output data rate. In many applications, the signal of interest represents a small proportion of the input BW. Spectrum occupancy is estimated by converting time domain signals at the output of DDC to frequency domain and applying detection threshold on the spectrum. This is achieved through Fast Fourier Transform (FFT) technique. Active signals within the pass band are detected based on the estimated Noise riding threshold of the spectral data. In this paper, DDC and FFT blocks are designed for implementation on FPGA. Vivado 2018.1 version tool is used in the design and development of the firmware. Broad specifications are RF = 100 to 1000 MHz, Second IF = 75 MHz, instantaneous BW = 40 MHz, ADC sampling rate, f s = 100 MHz.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.