Ever-increasing demand of computational capacity and power constraints of hand held and battery operated portable devices has lead to the requirement of Low power memories. The power consumption of SRAM varies widely depending on how frequently it is accessed; it can be as power-hungry as dynamic RAM, when used at high frequencies, and some ICs can consume many watts at full bandwidth. On the other hand, static RAM used at a somewhat slower pace, such as in applications with moderately clocked microprocessors, draws very little power and can have a nearly negligible power consumption when sitting idlein the region of a few micro-watts. Several techniques have been proposed to manage power consumption of SRAM-based memory structures. In this paper a robust adiabatic SRAM is designed. The main aim is to use adiabatic switching circuits to compensate throughput degradation, so a medium throughput for SRAM can be achieved. Proposed architecture is designed using adiabatic switching principles. Proposed adiabatic SRAM is tested using OrCAD Pspice. The results show that performance of adiabatic SRAM is better than other contemporary SRAMs
Power minimization is one of the primary concerns in today VLSI design methodologies because of two main reasons one is the long battery operating life requirement of mobile and portable devices and furthermore, the number of gates per chip area is constantly increasing, while the gate switching energy does not decrease at the same rate, so the power dissipation rises and heat removal becomes more difficult and expensive. In this paper a low power architecture for ASIP is proposed. Proposed architecture is designed using adiabatic switching principles. Proposed adiabatic ASIP is tested using VHDL. The results show that performance of adiabatic ASIP is better than other contemporary ASIPs
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