Under standard conditions, the electrostatic field-effect is negligible in conventional metals and was expected to be completely ineffective also in superconducting metals. This common belief was recently put under question by a family of experiments that displayed full gate-voltage-induced suppression of critical current in superconducting all-metallic gated nanotransistors. To date, the microscopic origin of this phenomenon is under debate, and trivial explanations based on heating effects given by the negligible electron leakage from the gates should be excluded. Here, we demonstrate the control of the supercurrent in fully suspended superconducting nanobridges. Our advanced nanofabrication methods allow us to build suspended superconducting Ti-based supercurrent transistors which show ambipolar and monotonic full suppression of the critical current for gate voltages of V G C ≃ 18 V and for temperatures up to ∼80% of the critical temperature. The suspended device architecture minimizes the electron−phonon interaction between the superconducting nanobridge and the substrate, and therefore, it rules out any possible contribution stemming from charge injection into the insulating substrate. Besides, our finite element method simulations of vacuum electron tunneling from the gate to the bridge and thermal considerations rule out the cold-electron field emission as a possible driving mechanism for the observed phenomenology. Our findings promise a better understanding of the field effect in superconducting metals.

We grow 28Si/SiGe heterostructures by reduced-pressure chemical vapor deposition and terminate the stack without an epitaxial Si cap but with an amorphous Si-rich layer obtained by exposing the SiGe barrier to dichlorosilane at 500 °C. As a result, 28Si/SiGe heterostructure field-effect transistors feature a sharp semiconductor/dielectric interface and support a two-dimensional electron gas with enhanced and more uniform transport properties across a 100 mm wafer. At T =  1.7 K, we measure a high mean mobility of [Formula: see text] cm2/V s and a low mean percolation density of [Formula: see text] cm−2. From the analysis of Shubnikov–de Haas oscillations at T =  190 mK, we obtain a long mean single particle relaxation time of [Formula: see text] ps, corresponding to a mean quantum mobility and quantum level broadening of [Formula: see text] cm2/V s and [Formula: see text] [Formula: see text], respectively, and a small mean Dingle ratio of [Formula: see text], indicating reduced scattering from long range impurities and a low-disorder environment for hosting high-performance spin-qubits.

Protein and DNA microarray chips enable the highly parallel investigation concerning the presence and amount of specific proteins or DNA sequences within a given sample. For this purpose, known probe molecules are immobilized on the chip surface, and binding events with matching target molecules from the sample are detected. Today, optical detection techniques are widespread ( Fig. 2.2.1, top). There, the target molecules are labeled with fluorescence markers. After the binding and a subsequent washing phase the chip is illuminated, and a fluorescence light image of the array reveals the positions with matching (i.e. chemically bound) probe and target molecules [1].In Fig. 2.2.1 (bottom), a fully electronic, label-free method is schematically depicted which circumvents expensive optical setups and lowers the biochemical complexity by avoiding the labeling step. The equivalent electrical impedance (modeled by R sens , C sens ) is dominated by the reactive component C sens , because R sens is very large (due to the quasi-ideal insulating properties of the electrode-solution interface [2]). Chemical binding events close to the surface of the sensor array electrodes lead to a sizable decrease of C sens [3].In this work, we present a 16×8 CMOS sensor array for detecting DNA hybridization based on capacitance measurements. A single sensor consists of two interdigitated gold electrodes. The electrode width and spacing are 1µm, the total sensor diameter is 200µm, and the sensor pitch is 300µm. Chips with a total area of 25mm 2 are fabricated in a 0.5µm, 5V standard CMOS process extended with extra steps to process the noble metal [5]. A chip micrograph with a blow-up of a single sensor is shown in Fig. 2.2.7.Figure 2.2.2 shows the capacitance measurement principle of the circuit underneath each sensor site. A constant current source (I ref ) is used to alternately charge / discharge the two terminals of the sensor. The voltage difference between the two terminals is monitored using a fully differential comparator. When this amplitude exceeds a defined threshold (V ref ), all switches change their state so that the charged (discharged) sensor terminal is discharged (charged) again, and the threshold voltage changes polarity. As a consequence, approximately triangular voltage waveforms are obtained at the sensor terminals V A and V B . The resulting frequency f of positive threshold crossings is measured by counting V out pulses. The resulting frequency f as a function of current and amplitude is given byFor not too low frequencies (i.e. not too low values of I ref ) the contribution of R sens is negligible and after some mathematics the approximation C sens = I ref / ( 2 V ref f ) is obtained for the interface capacitance. The frequency range used here is 500Hz to 1kHz. Figure 2.2.3 shows circuit design details. The sensor current I ref is provided by cascaded n-and p-MOS current sources. The p-MOS source is part of an in-sensor site p-MOS current mirror biased by an n-MOS current source.The n-MOS current sources bias vol...