Abstract-This article presents a new LowPass Delta SigmaModulators (LPDS) architecture to improve the noise shaping for high frequency applications. The errors resulting from approximations made by calculating with 1/2 N coefficients are compensated. Simulations with extracted parasitics of the layout are made and give a SNDR of 111dB, 3.8mW power consumption at 4GHz in 65nm CMOS technology for UMTS standard.
-In this paper, a method to study and characterize a single-loop, cascaded and 1-bit BandPass Delta Sigma modulator for digital transmitter is presented. This technique is based on a combination of digital filter simulation and nonlinear optimization of signal-to-quantization noise. The optimal coefficients of modulator structure are achieved by minimization of a quadratic criterion based on prediction error between desired digital filter and noise transfer model. To demonstrate the effectiveness of this approach, simulated results for a 6 th order cascaded structure for WCDMA Band-1 standard are presented. Spurious and ACLR improvement could be achieved for this standard with the proposed characterization technique.
In this paper, a method to study and characterize a single-loop, cascaded and 1-bit Band-Pass Delta Sigma (BP∆Σ) modulator for digital transmitter is presented. This technique is based on a combination of digital filter simulation and nonlinear optimization of signal-to-quantization noise. The optimal coefficients of BP∆Σ structure are achieved by minimization of a quadratic criterion based on prediction error between desired digital filter and noise transfer model. To demonstrate the effectiveness of this approach, simulated results for a 6 th order cascaded structure for WCDMA Band-1 standard are presented.
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