A subranging analog-to-digital converter (ADC) features high-speed and relatively low-power. The limiting factors of power reduction in subranging ADCs are the resistor ladder and the comparator. We propose an ADC architecture combining a capacitive digital-to-analog convertor and built-in threshold calibration to eliminate the resistor ladder, resulting in a low-power subranging ADC. We also propose a calibration technique comprising of metal-oxide-metal capacitor, MOS switch, and scaling capacitor to reduce the power consumption of the comparator and an offset drift compensation technique to enable precise foreground calibration. We designed an 8-bit, 1-GHz subranging ADC by applying these techniques, and post-layout simulation results demonstrated a power consumption of 7 mW and figure of merit of 51 fJ/conv.-step.
The offset drift of a dynamic comparator was analyzed using a simple model in order to clarify the offset drift mechanism. We found that it was possible to nullify the offset drift component due to size variability by controlling the gate common voltage (V com ). We conducted experiments to validate our estimations by using a test chip fabricated in 180-nm CMOS technology. Consequently, we found that the amount of variability of V TH and W/L could be extracted from the measured offset voltage. Moreover, the offset drift was reduced to 6.5 μV/°C by controlling the temperature dependence of V com .
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.