Neumann architectures to overcome the von Neumann bottleneck in artificial intelligence applications. [1][2][3][4][5][6][7][8] Neuromorphic architectures, especially spiking neural networks (SNNs), consume considerably less power (≈20 mW), than conventional von Neumann computing architectures (≈100 W). [9] As the main building block of SNNs, spiking neurons, especially complementary-metal-oxidesemiconductor field-effect transistor (C-MOSFET)-based neurons, have been intensively researched. However, the density of such neurons is limited because of the extremely large area of the capacitor (>500 μm 2 per capacitor) required to emulate the integrate function and achieve sufficient capacitance (i.e., several pF per capacitor). [10][11][12][13][14][15][16][17][18] To overcome this problem, the use of capacitor-less spiking neurons has been recommended. Recently, several researchers reported spiking neurons that can exhibit the integrate functionality, based on frameworks such as the phase-change memory, [19,20] resistive-random-access memory, [21][22][23][24][25] conductive-bridge-random-access memory, [26,27] and partially depleted silicon-on-insulator. [28] A spiking neuron principally needs a spike neuron device to emulate the integrate function and a sensing amplifier circuit to generate the fire function in a scheme known as integrate-and-fire. However, the existing studies only empirically presented spiking neuron devices to emulate the integrate function. Certain researchers designed a neuron in software by using a sense amplifier circuit, a controller for operating the neuron, a SNN containing neurons, and synapses, and a pattern recognition test was conducted using software simulations. However, only the realization of a spiking neuron was demonstrated as all the SNN operations based on spiking neuron devices emulating the integrate function were conducted via simulations.This study represents the first attempt at developing a conductive-bridge neuron emulating an integrate-and-fire function as an alternative to conventional C-MOSFET-based spiking neurons. The neuron was composed of a conductive-bridge-neuron device, sensing amplifier, and latch circuit. The conductivebridge-neuron device was fabricated in a simple manner by adopting a vertical device structure including a CuTe top electrode, TiO 2 resistive layer, and TiN bottom electrode. The Cu atoms diffused from the CuTe top electrode could easily form Cu filaments in the TiO 2 resistive layer. This phenomenon is of significance because Cu filaments in the TiO 2 resistiveThe neuronal density of complementary metal-oxide-semiconductor field-effect transistor-based neurons is limited because of the use of capacitors. Therefore, a novel neuron is fabricated using a conductive-bridge-neuron device, currentmirror-type sense amplifier, latch, micro-controller-unit, and digital-analogconverters. This neuron exhibits a typical integrate-and-fire function; in particular, the generation frequency of the fire spikes at the neuron exponentially increases with the i...
Recent research on artificial intelligence (AI) has focused on the computational performance of the human brain as a model to process large amounts of data to overcome the limits of current technology. [1,2] This is because the conventional von-Neumann architecture used to operate current AI algorithms causes a performance bottleneck between the computation required and the capacity of memory units. To achieve performance comparable to the biological brain using electronic devices, neuromorphic computing systems have been proposed. [3] This design, consisting of numerous artificial synapses that are essential for hardware advancement, has recently been demonstrated to have power-efficient computation and be extremely compact. [4] Therefore, the artificial synapse should be a simple twoterminal device to achieve brain-level (%10 15 synapses) compactness. Notably, artificial synaptic devices have low energy consumption for gradual conductance states to realize analog-like transitions, including long-term potentiation/longterm depression (LTP/LTD) and spike-timing-dependent plasticity. [5] Based on emerging nonvolatile memory technologies for realizing such characteristics, the devices are classified into phase-change synaptic devices, [6] resistive change synaptic devices, [7] and conductive-bridge synaptic devices relying on a physical switching mechanism. [8] Among them, phase-change synaptic devices have attracted attention because of their reliability and scalability down to the nanometer regime. [6,9] Ge 2 Sb 2 Te 5 alloys, a commonly used phase-change material, exhibit unique switching that creates a resistance difference between amorphous (RESET) and crystalline (SET) states by joule heating. However, a large electrical programming current pulse is needed for melting phase-change materials. Although several efforts have been made to reduce the RESET current, more energyefficient structures or materials are still needed, including stability improvements such as atomic migration, resistance drift, and phase segregation. [10] For this reason, an interfacial phase-change memory (iPCM) with a superlattice-like structure created by alternately depositing a GeTe thin film and Sb 2 Te 3 thin film was introduced by Tominaga et al. [11] The resistance difference is created by the behavior of Ge atoms in the GeTe film sandwiched by the van der Waals gap between the Sb 2 Te 3 films. Although the switching mechanism of iPCM has still not been elucidated, it operates at low energy consumption by restricting the atomic movement of Ge atoms. [12][13][14] Many approaches have been used to improve the properties of memory devices of the iPCM; however, the experimental configuration of an artificial synapse still needs to be investigated. In this article, we demonstrate the synaptic properties by fabricating different numbers of GeTe/Sb 2 Te 3 layers via sputtering.
The learning and inference efficiencies of an artificial neural network represented by a cross‐point synaptic memristor array can be achieved using a selector, with high selectivity (Ion/Ioff) and sufficient death region, stacked vertically on a synaptic memristor. This can prevent a sneak current in the memristor array. A selector with multiple jar‐shaped conductive Cu filaments in the resistive switching layer is precisely fabricated by designing the Cu ion concentration depth profile of the CuGeSe layer as a filament source, TiN diffusion barrier layer, and Ge3Se7 switching layer. The selector performs super‐linear‐threshold‐switching with a selectivity of > 107, death region of −0.70–0.65 V, holding time of 300 ns, switching speed of 25 ns, and endurance cycle of > 106. In addition, the mechanism of switching is proven by the formation of conductive Cu filaments between the CuGeSe and Ge3Se7 layers under a positive bias on the top Pt electrode and an automatic rupture of the filaments after the holding time. Particularly, a spiking deep neural network using the designed one‐selector‐one‐memory cross‐point array improves the Modified National Institute of Standards and Technology classification accuracy by ≈3.8% by eliminating the sneak current in the cross‐point array during the inference process.
Recently, a neuromorphic-chip performing artificial intelligence (AI) has been intensively for the application field of pattern recognition, autonomous car, etc. Biological neurons, which is able to be described hardware-wise by a cross-point synapse array being connected with input and output neurons like a vector multiplying arithmetic operation. The conventional neuromorphic-chip had been developed by a cross-point synapse array using C-MOSFET integrated circuit, where a synapse was realized by SRAMs while a neuron was achieved by an integration of C-MOSFETs and capacitors [1]. Thus, it presented a detrimental fault such as a large synapse and neuron size. As a solution, a cross-point synapse array using memristors has been researched popularly[2, 3]. However, it produced a sneak current during potentiating or depressing a selected memristor-synapse. To eliminate a sneak current in a memristor-based-synapse array, a n-MOSFET being connected with a synapse cell has proposed as a selector, but it has presented three terminals operating simultaneously a synapse-cell and a selector. Hence, recently, it has been intensively researched that a selector (S) is stacked vertically with a memristor-cell (M), called 1S1M-based synapse array, as shown in Fig. 1(a). In our study, a synapse array was fabricated with the HfO2 based memristor-cells being vertically stacked with super-linear threshold selectors, as shown in Fig. 1(b). The HfO2 based memristor showed 3-bit resistances for potentiation and depression, being adjusted by a reset voltage in the negative-resistance-region (NDR) of the memristor synapse, as shown in Fig. 1 (c). The potentiation and depression nature such as linearity and symmetry was estimated with the spike width of 100 μs and input spike number of 100, showing a good linearity (i.e., 3.27 for potentiation and -6.14 for depression) and symmetry nature (i.e., 0.12 ), as shown in Fig. 1(d). The memristor-synapse nature of 1S1M presented 3-bit resistances for potentiation and depression, the dead region between ~-0.40 and ~+0.42 V, the switching-on threshold voltages of ~-0.40 for negative applied bias and ~+0.42 V for positive applied bias, the set voltage of 0.92 V, and the reset voltage of -1.05 V, as shown in Fig. 1(e). This result well demonstrated a cross-point memristor-synapse array being able to operate a half-bias or 1/3-bias scheme writing. In addition, the effect of our proposed neural network on the pattern recognition accuracy was estimated by simulation. The cross-point neural network without a super-linear selector (i.e., 1M array), as shown in Fig. 1(f), was compared by that with a super-linear selector (i.e., 1S1M array), as shown in Fig. 1(g). Our proposed neuron was designed with a HfO2 based neuron having an integrate nature and a sense amplifier using 7 n-MOSFETs and 3 p-MOSFETs, as shown in Fig. 1(h). The neural network fabricated with 1S1M array and HfO2 based neurons showed ~10 % than that fabricated with 1M array and HfO2 based neurons, as shown in Fig. 1(i). This result indicates that the implementation of a super-linear threshold selector being vertically stacked on a memristor-synapse would be essentially necessary for a high accurate AI application. Acknowledgement This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIT) (No. 2016M3A7B4910249). This material is based upon work supported by the Ministry of Trade, Industry & Energy(MOTIE, Korea) under Industrial Technology Innovation Program (10068055). Reference [1] Merolla, Paul A., et al. "A million spiking-neuron integrated circuit with a scalable communication network and interface." Science 345.6197 (2014): 668-673. [2] Wu, Chaoxing, et al. "Flexible three-dimensional artificial synapse networks with correlated learning and trainable memory capability." Nature communications 8.1 (2017): 1-9. [3] Moon, K., et al. "RRAM-based synapse devices for neuromorphic systems." Faraday discussions 213 (2019): 421-451. Figure 1
Recently, the demand for more data storage and fast processing has been dramatically increased for the big data markets such as artificial intelligence (AI), virtual reality (VR), autonomous car, and internet of things (IoT). Thus, a new memory such as a storage class memory (SCM) has been introduced since it can perform a reasonable latency compared to DRAM and a lower bit-cost than NAND flash memory [1]. Remind that, generally, a SCM has been fabricated with three-dimensional cross point memory cell array [2]. As a candidate memory cell for SCM, resistive-random-access-memory (ReRAM) has been proposed; i.e., called storage-type SCM. Santini, C. A. et al. demonstrated amorphous carbon oxide (a-COx) based ReRAM-cell having a reasonable memory window margin (I on/I off > 100), a fast switching speed of 20~50 ns at ~ 100-nm-diameter memory cell size. However, it showed extremely a high forming voltage (V forming) of ~ 5.0 V and a high reset voltage (V reset) of ~ – 4.0 V [3]. In particular, the a-COx based ReRAM-cell presented a different bi-stable memory characteristic for another typical ReRAM-cells; i.e., its bias directions of set and reset were opposite to a typical ReRAM, which mechanism was not evidently proved. In addition, the forming process for this ReRAM cell would be highly undesirable since it caused an extra burden for initializing memory-cells and degraded the write and erase endurance cycles [4]. Here, for the first time, we designed a forming-free Cu-doped amorphous-carbon-oxide based ReRAM cell, which did not need a forming process and we reviewed the memory operation mechanism by understanding electrical and chemical properties of the Cu-doped a-COx based ReRAM cells. A typical a-COx based ReRAM-cell needed a forming process; i.e., a forming voltage of – 2.20 V and a set voltage of – 1.05 V, as shown in Fig. 1 (a). Otherwise, a Cu-doped a-COx based ReRAM-cell could achieve a forming-free process; i.e., a forming voltage (i.e. - 0.85 V) was the same as a set voltage (i.e. – 0.85 V), as shown in Fig. 1 (b). In addition, it demonstrated a write and erase endurance cycles of ~106 by sustaining a memory margin of ~1.3×102, being able to be utilized for a commercial nonvolatile memory-cell, as shown in Fig. 1(c). To clarify the forming-free mechanism, the depth profiles of C, Cu, and O atom in the Cu-doped a-COx memory cell were observed in detail under pristine, after set, and after reset process, which were obtained from intensity line-profiles of EELS/EDS elemental mapping images at C-K edges, O-K edges, Cu-Kα, Pt-La1, and W-La1. For the pristine state, C, Cu, and O atoms are uniformly distributed in the Cu-doped a-COx layer, as shown in Fig. 1(d). In addition, after a set process, since a negative voltage was applied to the top Pt electrode, Cu atoms evidently moved and segregated toward the top Pt electrode, as shown in a of Fig. 1(e), while O atoms evidently migrated and pile up toward the bottom W electrode, as shown in b of Fig. 1(e). This result means that the conductive C-C sp2 filaments in the Cu-doped a-COx layer were produced when oxygen atoms migrated and piled up toward bottom W electrode and the conductive Cu-atom filaments were formed in the Cu-doped a-COx layer since Cu atom moved and segregated toward the top Pt electrode. Hence, both conductive C-C sp2 filaments and Cu-atom filaments were generated simultaneously in the Cu-doped a-COx layer, achieving a set process without a forming process. On the other hand, after a reset process, since a positive voltage was applied to the top Pt electrode, Cu and O atoms were redistributed inside the Cu-doped a-COx, resulting in breaking both C-C sp2 filaments and Cu-atom filaments, as shown in a and b of Fig. 1(f). In our presentation, we will demonstrate and review the mechanisms between a set process without forming process and a reset process in detail by electrical and chemical composition depth profiles depending on the applied bias condition. In particular, we will demonstrate a different ReRAM behavior of the Cu-doped a-COx based ReRAM from a typical ReRAM or CBRAM. Acknowledgement This material is based upon work supported by the Ministry of Trade, Industry & Energy(MOTIE, Korea) under Industrial Technology Innovation Program (10068055). Reference [1] Matsui, C. et al. Integration 2019, 69, 62-74. [2] Hady, F. T. et al. Proceedings of the IEEE 2017, 105, (9), 1822-1833. [3] Santini, C. A. et al. Nature Communications 2015, 6, (1), 8600. [4] Skaja, K. et al. Scientific Reports 2018, 8. Figure 1
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