In order to analyze and recognize objects in binary images, two primary operations are required. First, component labeling is performed to identify objects with unique labels and to produce a labeled image. And boundary tracing is performed to form the ordered list of boundary position of object; which is a contour. These procedures are fundamental factors for image analysis. However, component labeling cannot be easily implemented in real-time because of the large size of image data and the high speed of image transition. In order to trace the object boundary every object's location are required, so boundary tracing is dependent on the component labeling which can determine the location of all objects. Therefore, we combine these two procedures in one dedicated hardware system. This system comprises the labeling component and tracing component. The labeling component identifies objects and produces the labeled image. By using this labeled image, the tracing component traces the boundary of identified object. Thus, the performance and efficiency of the binary image application can be increased. The system is implemented in a field programmable gate array (FPGA) by using the VHSIC hardware description language (VHDL). Experimental results and device utilization summary are given for the evaluation.
Connected component labeling is very useful for separating object and background, and counting objects. The sequential processing architecture proposed by Von Neumann has limits in real-time processing when large data is treated. In this study, a connected component labeling system using parallel hardware architecture is implemented. This system is able to calculate over 200 frames per second (fps) and is labeled a maximum of 255 components. This is a stand-alone system that can receive input image data from a camera and display the resulting image through a monitor.
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