The scheme of controlled collapse refiow chip joining has been investigated again and extended to the package of Josephson device chips. Low temperature ternary eutectic (In/Bi/Sn) alloy is selected as the solder material which melts at 60~ An interface metallurgy of Pd/Au was used as an interface layer bridging superconducting Nb pads and the solder. Indium stand-offs are used for controlling collapse and providing constant spacing between chips and carrier modules. Mechanical and electrical test vehicles were fabricated and evaluated.The controlled collapse reflow chip joining scheme used by IBM since the early days of the SLT package technology (1-6) has been extended, with some modifications, and adapted to the Josephson chip package. Josephson devices use Pb alloy films and thin oxide tunnel barriers at the junctions (7-9) which impose a temperature limitation and prevent the use of conventional Pb/Sn solder as in the silicon technology. 3o-sephson devices, which operate at 4.2 K, are subjected to thermal cycling between room temperature and 4.2 K, as compared with cycling of 60~ above ambient for silicon technology. Fast switching speed and high packing density permitted by the very low power dissipation (10) of the devices are the two most important features of Josephson technology. In order to fully utilize these advantages, terminated superconducting transmission lines over a super conducting ground plane (Nb) are used for package interconnection wiring (11). To satisfy the above conditions, a chip bonding technology utilizing the controlled collapse chip joining scheme was adapted. Other convert, tional methods, for example, wire bonding, were not acceptable due to excess inductance and time delay. This paper considers the choice of solder alloy, interface metallurgy, processing and fabrication techniques, test vehicles, and their test results.
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