Electrical Integrity of State-of-the-Art 0.13 prn SO1 CMOS Devices a n d Circuits T r a n s f e r r e d f o r Three-Dimensional (3D) I n t e g r a t e d C i r c u i t (IC) Fabrication
AbstractWe introduce a new scheme for building threedimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the fmt time that the processes required for stacking active device layers preserve the intrinsic electrical characteristics of stateof-the-art short-channel MOSFETs and ring oscillator circuits, which is critical to the success of high performance 3D ICs.
Schottky diodes fabricated on in situ doped n-type Si/Si1−x−yGexCy/Si heterostructures grown by chemical vapor deposition were used for admittance spectroscopy in order to study the impact of carbon on the conduction band offsets. Samples with a nominal Ge concentration of 20 at. % and carbon fractions up to 1.3 at. % were studied. In these experiments, the measurement frequency was swept continuously from 1 kHz to 5 MHz, and the temperature was scanned in small increments from 20 to 300 K. Admittance signals in these samples were found to originate from three sources, namely doping freeze-out, band offsets, and traps. Signals arising from the band offsets indicate a conduction band edge lowering for Si/Si1−x−yGexCy of ∼33±22 meV/at. % C. A trap-related admittance signal at an energy of 228±25 meV below the Si conduction band was observed in the Si1−x−yGexCy sample with the highest C fraction (1.3 at. %). The trap energy measured by admittance spectroscopy is in close agreement with the activation energy of 230 meV, which has been reported in the literature for a complex involving interstitial carbon. The conduction band offset in a Si/Si1−yCy sample with 0.95 at. % C was also measured by both admittance spectroscopy and Schottky capacitance–voltage profiling. The two techniques yield excellent agreement, with Si/Si0.9905C0.0095 conduction band offsets of 48±10 and 55±25 meV, respectively.
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