In today's access networks, the permutation of circuits connecting the subscriber lines to Plain Old Telephone Service (POTS) and to Digital Subscriber Line Access Multiplexers (DSLAMs) occurs in the Main Distribution Frame (MDF) and is still manually configured. However, new market regulations and new policies adopted by operators require increasingly more frequent permutations, making the manual configuration activity particularly expensive. Very recently, Automated MDFs (AMDF) have been developed to provide inexpensive and almost real-time switching capability. Our study, based on more than 50 years of research activities on architectures for circuit switching, is focused on overcoming the limits of classical architectures. In fact, strictly non-blocking multistage networks are too expensive, as a consequence of the large number of ports they require (sometimes exceeding 100,000). In addition, rearrangeable multistage networks can temporarily interrupt active circuits, affecting the performance of ADSL subscriber lines.As a possible solution to these problems, we propose the design of AMDFs based on Non-Interruptive Rearrangeable (NIR) networks. We show how to optimize the routing control to minimize the setup time of a circuit and to exploit output grouping. We believe that the solution described above is not only relevant for the theory of multistage interconnection networks, but also for the design and operation of large AMDFs.
Input-queued (IQ) switches are one of the reference architectures for the design of high-speed packet switches. Classical results in this field refer to the scenario in which the whole switch transfers the packets in a synchronous fashion, in phase with a sequence of fixed-size timeslots, selected to transport a minimum-size packet. However, for switches with large number of ports and high bandwidth, maintaining an accurate global synchronization and transferring all the packets in a synchronous fashion is becoming more and more challenging. Furthermore, variable size packets (as in the traffic present in the Internet) require rather complex segmentation and reassembly processes and some switching capacity is lost due to partial filling of timeslots. Thus, we consider a switch able to natively transfer packets in an asynchronous fashion thanks to a simple and distributed packet scheduler. We investigate the performance of asynchronous IQ switches and show that, despite their simplicity, their performance are comparable or even better than those of synchronous switches. These partly unexpected results highlight the great potentiality of the asynchronous approach for the design of high-performance switches.
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