SUMMARYThe load balanced Birkhoff-von Neumann switch is an elegant VOQ architecture with two outstanding characteristics: (i) it has a computational cost of Oð1Þ iterations and (ii) input controllers do not exchange information (as a result, it allows decoupled implementations with a low power density). The load balancing stage guarantees stability under a broad class of traffic patterns. It may alter packet sequence, but this can be solved with appropriate packet selection strategies.The average packet delay caused by previous maximal size matching algorithms, such as iSLIP, RDSRR, or PHM is noticeably lower than that of a Birkhoff-von Neumann switch, especially for low and medium loads. However, they need tightly coupled VOQ controllers, which implies higher power density. For example, this makes difficult to apply those algorithms to optical switching architectures. Moreover, they require Oðlog 2 NÞ iterations to converge, and this computational cost may be unacceptable for the slot lengths in optical packet switches.In this paper, we propose a family of decoupled Parallel Hierarchical Matching (PHM) VOQ controllers (DPHM). They outperform the Birkhoff-von Neumann scheduler, which can be viewed as a member of the family (in fact, the simplest one). DPHM schedulers have a computational cost of Oð1Þ iterations and, unlike last generation maximal size matching algorithms, they allow a low input controller interconnection complexity (low power density switch implementation).
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Abstract. In this paper we propose an enhanced parallel iterative scheduler for IBWR synchronous slotted OPS switches in SCWP mode. It obtains a maximal matching of packet demands without resource conflicts. The analytical and numerical results are highly competitive regarding previous work.
SUMMARYIn this paper we propose a novel scheduling approach for optical packet switching (OPS) WASPNET nodes, LBWS. Unlike the original WASPNET description, our scheduler is fully distributed and its computational cost is independent from switch size. This allows shorter packets, improving network performance. Based on a deterministic evolution of the switch configuration, our scheduling algorithm predicts packet delays at packet ingress to guarantee switch stability, and assigns fibre delay lines (FDLs) accordingly. It is not necessary to emulate RAM memories, since we assign delay lines according to packet delay predictions. We demonstrate that LBWS outperforms WASPNET in the cases studied, for nonuniform input traffic.
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