This paper proposes a single-stage asymmetrical half-bridge fly-back (AHBF) converter 11 with resonant mode using dual-mode control. The presented converter has an integrated boost 12 converter and asymmetrical half-bridge fly-back converter and operates in resonant mode. The 13 boost-cell always operates in discontinuous conduction mode (DCM) to achieve high power factor.
14The presented converter operates simultaneously using a variable-frequency-controller (VFC) and
This paper proposes a single-stage asymmetrical half-bridge fly-back (AHBF) converter with resonant mode using dual-mode control. The presented converter has an integrated boost converter and asymmetrical half-bridge fly-back converter and operates in resonant mode. The boost-cell always operates in discontinuous conduction mode (DCM) to achieve high power factor. The presented converter operates simultaneously using a variable-frequency-controller (VFC) and pulse-width-modulation (PWM) controller. Unlike the conventional single-stage design, the intermediate bus voltage of this controller can be regulated depending on the main power switch duty ratio. The asymmetrical half-bridge fly-back converter utilizes a variable switching frequency controller to achieve the output voltage regulation. The asymmetrical half-bridge fly-back converter can achieve zero-voltage-switching (ZVS) operation and significantly reduce the switching losses. Detailed analysis and design of this single-stage asymmetrical half-bridge fly-back converter with resonant mode is described. A wide AC input voltage ranging from 90 to 264 V rms and output 19 V/120 W prototype converter was built to verify the theoretical analysis and performance of the presented converter.
A pair of complementary class-A buffers with voltage boosting method and improved frequency compensation is proposed. The buffer driving capabilities are enhanced by adding small auxiliary transistors to pull-up/pull-down the gate voltages of the buffer output transistors to improve the transient response. The auxiliary transistors are turned off for power saving in the steady-state operation. The proposed frequency compensation is more area-efficient than the Miller compensation method and hence maintains the high output voltage slew rate of the buffer. The measured static current of each buffer with the proposed circuits consumes 3 μA under a supply voltage of 5 V. The buffer settling times of the rising and the falling edges with a capacitance of 600 pF for an input swing of 5 V are 3.3 and 1.7 μs, respectively. The core size of the buffers including the compensation capacitance is 82 × 101 µm 2 and the buffer can be stable when a load capacitance changes from 5 to 600 PF. Hence, the proposed output buffers concurrently achieve a fast response and are suitable for a wide range of load capacitances.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.