A new PDP cell structure called CSP (Charge Storage Pad) improves the luminous efficiency by 1.6 times and prevents cross talk between adjacent cells. The CSP, which is a conducting material, is inserted between the dielectric layer and the MgO film in the front plate. This CSP produces a longer time-averaged discharge path to get a high luminous efficiency and confines the discharge to prevent cross talk
A single wafer cleaning system with full coverage back-side megasonics has been developed for pre-lithography backside cleaning processes. Backside particle removal efficiency (PRE) of >95% at ≥65nm for Si 3 N 4 particles was achieved with DIW only, demonstrating enhanced particle removal at both smaller and larger particle sizes with full coverage megasonics. PRE values of >99% were attained by using dilute HF/SC1 chemistry and by increasing megasonics power with SC1. The single wafer clean system allows DIW to be dispensed on the frontside if desired to minimize chemical contact on the device side of the wafer while chemistry is applied to the backside. Etch rate tests confirmed no flow of chemistry to the frontside of the wafer. Field data have shown that full coverage megasonics cleaning can reduce the maintenance frequency of lithography tools. Wafers processed with conventional megasonics or non-megasonics processes encountered subsequent chucking or focusing problems resulting in significant down time of the lithography tool, whereas these issues were not encountered for those wafers cleaned with full coverage megasonics.
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