a full wave modelling approach based on authors' previous work is improved to model DC blocking capacitor. By correlating to the measurement data, it is shown that the modelling approach is accurate. A methodology of developing equivalent capacitor model for signal integrity simulation is proposed to improve simulation efficiency. In order to mitigate the impact from DC blocking capacitor, voiding is studied to find optimal voiding scheme. Full link PCIE Gen 3 simulations is performed as an example to demonstrate design optimization for AC coupling high-speed links and some rules of thumb are derived based on the study.

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In this paper a transmission line of fmite length conductor with bend is considered. Explicit expressions for the per-unit-length parameters of the line are derived by using non-uniform transmission line approach and are verified by the method of moment.

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For high speed signaling, 100Ohm differential impedance has been commonly used for decades. In recent years, 85Ohm differential impedance has been adopted for PCIE Gen2 and Gen3 for better signal integrity performance and routing consideration. However, for storage IOs such as SATA and SAS, buffer, cable, and connector, etc, are 100Ohm design. It is not clear whether we still have better signal integrity performance using 85 ohm package and motherboard routing. In this paper, we will report simulation and measurement results for 3Gbps and 6Gbps SATA and SAS links, by comparing 85Ohm package and mother routing with 100Ohm routing. Results show that 85Ohm package and motherboard routing have better signal integrity performance than 100Ohm even if cable, connector, hard disk driver and buffer, etc, are all designed at 100Ohm. Our conclusion is very meaningful in defining interconnect impedance for new generation of storage IO specification such as SAS 12Gbps.

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