Rodent electroencephalography (EEG) in preclinical research is frequently conducted in behaving animals. However, the difficulty inherent in identifying EEG epochs associated with a particular behavior or cue is a significant obstacle to more efficient analysis. In this paper we highlight a new solution, using infrared event stamping to accurately synchronize EEG, recorded from superficial sites above the hippocampus and prefrontal cortex, with video motion tracking data in a transgenic Alzheimer's disease (AD) mouse model. Epochs capturing specific behaviors were automatically identified and extracted prior to further analysis. This was achieved by the novel design of a ultraminiature wearable EEG recorder, the NAT-1 device, and its insitu IR recording module. The device is described in detail, and its contribution to enabling new neuroscience is demonstrated.

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0000-0003-0613-9698, Dai, Chengliang and Austin, James orcid.org/0000-0001-5762-8614 (2019) A 65nm CMOS lossless bio-signal compression circuit with 250 femtoJoule performance per bit. IEEE Transactions on Biomedical Circuits and Systems. pp.Abstract-A 65nm CMOS integrated circuit implementation of a bio-physiological signal compression device is presented, reporting exceptionally low power, and extremely low silicon area cost, relative to state-of-the-art. A novel 'xor-log2-subband' data compression scheme is evaluated, achieving modest compression, but with very low resource cost. With the intent to design the 'simplest useful compression algorithm', the outcome is demonstrated to be very favourable where power must be saved by trading off compression effort against data storage capacity, or data transmission power, even where more complex algorithms can deliver higher compression ratios. A VLSI design and fabricated Integrated Circuit implementation are presented, and estimated performance gains and efficiency measures for various bio-medical use-cases are given. Power costs as low as 1.2 pJ per sample-bit are suggested for a 10kSa/s data-rate, whilst utilizing a power-gating scenario, and dropping to 250fJ/bit at continuous conversion data-rates of 5MSa/sec. This is achieved with a diminutive circuit area of 155 um 2 . Both power and area appear to be state-of-the-art in terms of compression versus resource cost, and this yields benefit for system optimization.