Reset is one of the most important signals in many designs. Since reset is typically not timing critical, it is handled at late physical design stages. However, the large fanout of reset and the lack of routing resources at these stages can create variant delays on different targets of the reset signal, creating reset recovery problems. Traditional approaches address this problem using physical design methods such as buffer insertion or rerouting. However, these methods may invalidate previous optimization efforts, making timing closure difficult. In this work we propose a formal method to calculate reset recovery slacks for registers at the register transfer level. Designers and physical design tools can then utilize this information throughout the design flow to reduce reset problems at later design stages.978-3-9810801-7-9/DATE11/ c 2011 EDAA
In a noisy quantum channel, burst errors usually causes multiple bit-phase flips that are adjacent to each other [1-2]. This effectively makes some quantum error-correcting codes to be unusable. In this paper, the concept of interleaving qubit transmission is proposed. By using the interleaving method in a quantum information transmission process, burst errors in a quantum channel are re-arranged into different time slots. This relocation makes the error bits non-adjacent and hence increases the probability of information recovery. Note that although this scheme enhances the error-correcting capability of the encoded quantum information, it does not increase the redundancy of the code, because only the qubit sequences are relocated. In addition to the interleaving scheme, implementation of the proposed scheme at the circuit level is also discussed in this paper.
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