The continuous scaling of CMOS technology increases processor performance and memory capacity, requiring the CPU/Memory interface to have ever-higher bandwidth and energy efficiency over the past few years. Among those cuttingedge interface technologies, multi-band (multi-tone) signaling has shown great potential because of its high data-rate capability along with its low energy consumption [3]- [5]. With spectrally divided signaling, the multi-band transceiver can be designed to avoid spectral notches with extended communication bandwidth of multi-drop buses [4]. Also, its unique self-equalized doublesideband signaling renders the multi-band transceiver immune to inter-symbol interference caused by channel attenuation without additional equalization circuitry [5]. To further improve the capability and validate the scalability of multi-band signaling, we have realized a tri-band transceiver with four parallel lanes and achieved a total data rate of 40Gb/s, with total power consumption of 38mW in 28nm CMOS technology.To obtain the total data rate of 40Gb/s, PAM-4 and 16-QAM are adopted at the baseband and 3/6GHz RF bands, respectively, to carry ten parallel bit streams at a modest 1GHz symbol rate via each lane of the transceivers ( Fig. 10.2.1). These ten parallel bit streams share the same physical channel to minimize the timing skew among them. With this benefit, we can assign one of the ten bits as DQS for each lane so that no deskew circuitry is needed for data recovery at the receiving end. Both upper and lower images of the original signal exist after upconverting with 16-QAM at 3/6GHz RF bands. The lower sideband with less attenuation compensates for the upper sideband with more attenuation and thus the demodulated signal is evenly attenuated over frequencies. Consequently, insignificant inter-symbol interference is induced and no equalization circuitry is necessary in this system.The transmit end (TX) consists of five identical paths, each with one 2b DAC, one fully differential mixer and one current-mirror output buffer ( Fig. 10.2.2). The 2b DAC is designed with bottom current of I ref at each end to ensure the output buffer can operate up to 6GHz. The clock inputs of the baseband mixer are tied to logic high and logic low so that the output signal remains at the baseband. The clock inputs of the other four mixers are separately connected to four carriers generated from a single external 12GHz reference with two cascaded divide-by-2s. The four carriers are I/Q at 3GHz and 6GHz, respectively. A fully differential architecture is used to suppress even-order harmonics and reduce interference from 3GHz to 6GHz. The entire carrier generator is based on CML to ensure its clock duty cycle error to be less than ±1%, inducing a signal-to-interference ratio (SIR) of >30dB. Finally, a digitally controlled phase interpolator is utilized for phase calibration at the receiving end in order to retrieve correct data from 16-QAM signals. At the receiving end (RX), a gain-reused regulated cascode is used as an input buff...
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