CD control specifications for poly gate patterning are becoming tighter and tighter: latest revisions of International Technology Roadmap for Semiconductors require a CD control in the range of 2.2nm (3σ) for the 65nm technology node. In this scenario model-based Optical Proximity Correction methodologies, traditionally developed to address optical and resist development effects, had to face the challenge to correct post-resist processing steps with the aim to guarantee a final effective CD control within expected specifications. Complex 1D rule-based corrections, applied in the past, are no more adequate to capture complex 2D effects becoming relevant starting from 90nm node; only a more comprehensive 2D model-based approach can correctly predict, and so compensate, complex physical and chemical etch phenomena inducing CD variations. In this paper we experimentally study the impact of medium and long range etch effects on poly gate patterning, trying to identify their nature and impact on intra-die CD variations. Different innovative model-based approaches for lithography and etch effects compensation are evaluated and compared on Flash memory circuitry (90, 65 and 45 nm node) with the aim to reduce intra-die CD dispersion component. Finally the impact of local and global pattern density on etch behavior is studied in relation to different dummy placement strategies.
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