This paper describes the design of a four-valued memory cell based on a three-peak MOS-NDR circuit.We connect three MOS-NDR devices in parallel that can create a three-peak current-voltage curve by suitably arranging the parameters. Due to its folding I-V characteristics, multiple -peak NDR device is a very promising device for multiple -valued logic application. This memory cell structure can be easily extended to implement more states in a memory circuit.
We present three oscillator designs using the negative-differential-resistance (NDR) circuit which is composed of several Si-based metal-oxide-semiconductor field-effect transistor (MOS) devices and one SiGe-based heterojunction bipolar transistor (HBT) devices. These oscillator circuits are composed of the NDR circuit, resistor, inductor, and capacitor. The oscillation frequencies are about several GHz based on the HSPICE simulation results. The circuits are designed using a standard 0.18 μm BiCMOS technique. Because our circuits are mainly made of a BiCMOS-NDR circuit that is different from a tradition NDR device made by a resonant tunneling diode with a quantum-well structure, we can utilize the nanobased BiCMOS process to implement these circuits by further improving the parameters.
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