Instead of the conventional furnace annealing process with a temperature higher than 300°C, two low temperature annealing methods are successfully demonstrated to suppress the instability problem of amorphous indium gallium zinc oxide ͑IGZO͒ thin film transistors ͑TFTs͒. With adequate Nd:yttrium aluminum garnet laser ͑266 nm͒ annealing energy density or Xe excimer UV lamp ͑172 nm͒ irradiation time, the on voltage shift is greatly suppressed from over 10 to 0.1 V. The influence of laser energy density and UV lamp irradiation time on the performance of IGZO TFTs is also investigated and explained. The proposed methods are promising for the development of amorphous IGZO TFTs on flexible substrates.Recently, transparent amorphous InGaZnO 4 ͑IGZO͒ thin-film transistors ͑TFTs͒ have become promising candidates to realize flexible display on plastic substrates because they can be deposited at a temperature lower than 150°C. 1 Compared to amorphous silicon TFT, IGZO TFT exhibits a higher mobility ͑3-30 cm 2 /V s͒ even in the amorphous phase. 2 However, in many articles, low temperature deposited IGZO TFT suffers from significant instability problems. 3,4 Its current-voltage ͑I-V͒ characteristics shift during electrical measurement. To suppress the characteristics' shift, furnace annealing higher than 300°C is usually used. It was reported that the annealing process reduces the tail state defects, rearranges the amorphous structure, and improves oxygen compensation in the nonstoichiometric film. 3,4 However, an annealing temperature higher than 300°C makes the process unsuitable for flexible substrates. A low temperature annealing process is essential for the development of stable IGZO TFTs on flexible substrates.One method utilizing excimer laser annealing ͑ELA͒ to improve IGZO TFT characteristics was proposed recently. 5 Although the authors did not mention stability issues, they successfully demonstrated the feasibility of using ELA on IGZO TFTs. In our study, two low temperature annealing methods are proposed to effectively solve the stability problem. One method is the solid-state Nd:yttrium aluminum garnet ͑YAG͒ laser annealing method; the other method is a simple UV lamp irradiation method. The Nd:YAG solid-state laser operates at a wavelength of 266 nm, annealing the IGZO TFT at a low laser energy density of 10.7 mJ/cm 2 . This low energy density enables the future design of a large laser beam size with a low production cost. To further reduce the production cost, another annealing process is proposed. This annealing process uses a low power ͑50 mW/cm 2 ͒ Xe excimer lamp with a wavelength of 172 nm ͑UV light͒. The UV lamp irradiation effectively anneals the devices. The proposed method is a promising candidate to realize large-area, low cost UV lamp annealing for IGZO TFTs. In this article, the influences of laser energy density and UV lamp irradiation time on the performance and stability of IGZO TFTs are investigated. The bias-stress effects of an unannealed device, a laserannealed device, and a UV-annealed devic...

No abstract

This work presents a method for enhancing the mobility of polycrystalline-Si ͑poly-Si͒ thin-film transistors ͑TFTs͒ by pattern-dependent metal-induced-lateral-crystallization ͑PDMILC͒ using nanowire channels. Experimental results indicate that the field-effect mobility of PDMILC TFT was enhanced as the channel width decreased, because the lateral length of the poly-Si grains increased. The PDMILC poly-Si TFT with ten nanowire channels ͑M10͒ had the greatest field-effect mobility, 109.34 cm 2 / V s and the lowest subthreshold swing, 0.23 V / dec, at a gate length of 2 m. The field-effect mobility also increased as the gate length in the M10 PDMILC poly-Si TFT device declined, because the number of poly-Si grain-boundary defects was reduced.

This work studied the effects of channel width and NH 3 plasma passivation on the electrical characteristics of a series of pattern-dependent metal-induced lateral crystallization ͑PDMILC͒ polysilicon thin-film transistors ͑poly-Si TFTs͒. The performance of PDMILC TFTs improves as each channel width decreasing. Further, PDMILC TFTs with NH 3 plasma passivation outperforms without such passivation, resulting from the effective hydrogen passivation of the grain-boundary dangling bonds, and the pile-up of nitrogen at the SiO2/poly-Si interface. In particular, the electrical characteristics of a nanoscale TFT with ten 67 nm wide split channels ͑M10͒ are superior to those of other TFTs. The former includes a higher field effect mobility of 84.63 cm 2 /V s, a higher ON/OFF current ratio ͑Ͼ10 6 ͒, a steeper subthreshold slope ͑SS͒ of 230 mV/decade, and an absence of drain-induced barrier lowering ͑DIBL͒. These findings originate from the fact that the active channels of the M10 TFT have exhibit the most poly-Si grain enhanced to reduce the grain boundary defects and the best NH 3 plasma passivation. Both effects can reduce the number of defects at grain boundaries of poly-Si in active regions for high performances.The major attraction of applying polycrystalline silicon thin-film transistors ͑poly-Si TFTs͒ in active matrix liquid crystal display ͑AMLCDs͒ lies in the greatly improved carrier mobility ͑larger than 10 cm 2 /V s͒ in poly-Si film and the capability of integrating the pixel switching elements, the panel array, and the peripheral driving circuit on the same substrate, 1-3 bring the era of system-on-panel ͑SOP͒ technology. For making high performance poly-Si thin film transistors ͑TFTs͒, low-temperature technology is required for the realization of commercial flat-panel displays on inexpensive glass substrates, which the maximum process temperature is limited to less than 600°C. There are three major low-temperature amorphous-Si crystallization methods to achieve high performance poly-Si thin film: solid phase crystallization ͑SPC͒, 4 excimer laser crystallization ͑ELC͒, 5 and metal-induced lateral crystallization ͑MILC͒. 6-10 MILC technology was initially developed as a lowtemperature crystallization technique compared to other lowtemperature poly-Si technologies such as ELC or conventional SPC. MILC is superior because, unlike ELC, it is a low-cost batch process and, unlike SPC, a better quality poly-Si thin film can be obtained. In addition, the presence of poly-Si grain boundary defects in the channel region of TFTs drastically affects the electrical characteristics, especially when the device dimension is scaled down. Therefore, reducing the number of polysilicon grain boundary defects will improve the performance of poly-Si TFTs. The poly-Si TFTs with several multichannels have been reported to effectively reduce grain boundary defects. 11,12 Thus, we demonstrate a practicable method to reduce the poly-Si grain boundary defects by using a structure modulation MILC process ͑i.e., PDMILC͒ to fabricate the h...