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This paper presents a real-time high-definition 720p@30fps H.264/MPEG-4 AVC intra-frame codec IP suitable for digital video and digital still camera applications. The whole design is optimized in both the algorithm and architecture levels. In the algorithm level, we propose to remove the area-costly plane mode, and enhance the cost function to reduce hardware cost and to increase the processing speed while provide nearly the same quality. In the architecture design, in additional to the fast module implementation the process is arranged in the macroblock-level pipelining style together with three careful scheduling techniques to avoid the idle cycles and improve the data throughput. The whole codec design only needs 103 K gate count for a core size of 1.28 1.28 mm 2 and achieves real-time encoding and decoding at 117 and 25.5 MHz, respectively, when implemented by 0.18-m CMOS technology. Index Terms-Highdefinition, intra-frame codec, ISO/IEC 14496-10 AVC, ITU-T Rec. H.264, Joint Video Team (JVT).

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