The opening of spectral bands in the millimeter-wave (mm-Wave) spectrum from 26 GHz and extending up to the E-band poses new challenges to the power amplifier (PA) design for spectrally agile radios. They are expected to operate with high energy efficiency at peak and back-off levels to process signals with high peak-to-average power ratio (∼10 dB), while being able to maintain their performance across a wide range of 5G bands. In addition, the PAs can experience strong load impedance mismatch conditions in a user equipment (UE) that pose additional challenges in handling strong voltage-standing-wave-ratio (VSWR) events. In this article, we present a systematic approach to exploit active load pulling in a multi-port network that synthesizes optimal impedance conditions for 1) broadband peak and back-off operation and 2) mitigating VSWR events at peak power. As proofs of concept, we present two PAs in 65-nm bulk CMOS process. The first chip demonstrates P sat between 16.3 and 19.3 dBm across 37-73 GHz, with an improvement in the output drain efficiency (η out ) of up to 3.2×/5.8× at 6-/9.6-dB power back-off (PBO) across the frequency range compared to class-A operation. The second chip achieves 26-42-GHz P sat, −1 dB bandwidth with P sat > 19 dBm and PAE peak > 20% across all 28-40-GHz bands and with up to 3.35× and 4.84× enhancement in PAE at the PBO levels of 6 and 9.6 dB over class-A operation, respectively. The PA also demonstrates strong tolerance to VSWR events with only 2 dB degradation over a VSWR 4:1 load circle at a frequency of 33 GHz.

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