The main objective of this study was to enhance the performance of sleep stage classification using single-channel electroencephalograms (EEGs), which are highly desirable for many emerging technologies, such as telemedicine and home care. The proposed method consists of decomposing EEGs by a discrete wavelet transform and computing the kurtosis, skewness and variance of its coefficients at selected levels. A random forest predictor is trained to classify each epoch into one of the Rechtschaffen and Kales' stages. By performing a comprehensive set of tests on 106,376 epochs available from the Physionet public database, it is demonstrated that the use of these three statistical moments has enhanced performance when compared to their application in the time domain. Furthermore, the chosen set of features has the advantage of exhibiting a stable classification performance for all scoring systems, i.e., from 2- to 6-state sleep stages. The stability of the feature set is confirmed with ReliefF tests which show a performance reduction when any individual feature is removed, suggesting that this group of feature cannot be further reduced. The accuracies and kappa coefficients yield higher than 90 % and 0.8, respectively, for all of the 2- to 6-state sleep stage classification cases.

No abstract

This paper proposes topological enhancements to increase voltage gain of ultra-low-voltage (ULV) inverter-based OTAs. The two proposed improvements rely on adoption of composite transistors and forward-body-biasing. The impact of the proposed techniques on performance figures is demonstrated through simulations of two OTAs. The first OTA achieves a 39 dB voltage gain, with a power consumption of 600 pW and an active area of 447 μm2. The latter allies the forward-body-bias approach with the benefit of the independently biased composite transistors. By combining both solutions, voltage gain is raised to 51 dB, consuming less power (500 pW) at the cost of an increased area of 727 μm2. The validation has been performed through post-layout simulations with the Cadence Analog Design Environment and the TSMC 180 nm design kit, with the supply voltage ranging from 0.3 V to 0.6 V.

This paper presents the design of a low-power high-CMRR CMOS instrumentation amplifier (IA) aimed for biomedical applications. The amplifier fundamentals were initially presented followed by its main building blocks. Simulation and experimental results were presented and discussed. The IA circuit was designed in AMIS 1.5 µm technology and manufactured through the MOSIS Service. The measured gain,CMRR and power consumption were 65dB, 120dB and 100uW respectively

Introduction: In this paper we propose a promising new technique for drowsiness detection. It consists of applying the best m-term approximation on a single-channel electroencephalography (EEG) signal preprocessed through a discrete wavelet transform. Methods: In order to classify EEG epochs as awake or drowsy states, the most significant m terms from the wavelet expansion of an EEG signal are selected according to the magnitude of their coefficients related to the alpha and beta rhythms. Results: By using a simple thresholding strategy it provides hit rates comparable to those using more complex techniques. It was tested on a set of 6 hours and 50 minutes EEG drowsiness signals from PhysioNet Sleep Database yielding an overall sensitivity (TPR) of 84.98% and 98.65% of precision (PPV). Conclusion: The method has proved itself efficient at separating data from different brain rhythms, thus alleviating the requirement for complex post-processing classification algorithms.

This paper deals with a single-stage single-ended inverter-based Operational Transconductance Amplifiers (OTA) with improved composite transistors for ultra-low-voltage supplies, while maintaining a small-area, high power-efficiency and low output signal distortion. The improved composite transistor is a combination of the conventional composite transistor and forward-body-biasing to further increase voltage gain. The impact of the proposed technique on performance is demonstrated through post-layout simulations referring to the TSMC 180 nm technology process. The proposed OTA achieves 54 dB differential voltage gain, 210 Hz gain–bandwidth product for a 10 pF capacitive load, with a power consumption of 273 pW with a 0.3 V power supply, and occupies an area of 1026 μm2. For a 0.6 V voltage supply, the proposed OTA improves its voltage gain to 73 dB, and achieves a 15 kHz gain–bandwidth product with a power consumption of 41 nW.

An instrumentation amplifier based on constant gm, rail-to-rail transconductance amplifiers is presented. The circuit was designed to 0.5,um AMIS C5 CMOS technology. Simulation results show that a -3dB bandwidth about 190 kHz could be obtained. Operating with a 3V supply and its dc gain set to 66 dB, the amplifier has a power consumption of 110,uW, and a CMRR higher than 140dB.I.

No abstract