This paper describes the design and development of an Application Specific Integrated Circuit (ASIC) to implement the filtering and AGC sections of a new digital approximation to the Lyon/Mead Analog Cochlea Model [1,2]. The ASIC uses a fully synchronous bit-serial design methodology originally developed for MOS technologies by h y e r and Renshaw [3] and adapted subsequently for use with low cost standard cell design tools by Summerfield and Jabri [4]. The resulting device is an example of a new class of signal processing ASIC, referred to as an Application Specific Signal Processor (ASSP). As well as presenting details of the filter and AGC structure of the new cochlea model, the paper describes the bit-serial design methodology used to implement the algorithm in real-time and in low cost ASIC form. The approach is a generic one and can be applied to a wide range of speech signal processing functions. MTRODUCTIONCochlea models are widely studied by the speech research community for speech analysis and recognition. In addition, the Lyomead analog cochlea model is interesting for its implications on hearing research, since it displays nonlinear gain adaptation at the mechanical filtering level. One of the long term attractions of cochlea model based signal processing is the promise of increased recognition performance, especially in variable and high noise environments. Algorithms motivated by cochlea processing, notably those developed by Ghitza and Seneff, have demonstrated some degree of improvement on restricted recognition tasks [5, 6, 71.One of the difficulties with implementing many of these more elaborate signal processing algorithms, in practical systems, is the problem of achieving real-time performance using conventional programmable Digital Signal Processing (DSP) technologies in a cost effective form, A novel solution adopted by Lyon and Mead [1,2] has been the implementation of these functions using sub-threshold analogue VLSI techniques. Although this produces extremely small and efficient circuits, the approach, as yeb is not compatible with standard design and characterization tools, test and adjustment techniques, and other standard practices. An altemative approach, described in this paper, utilises a fully synchronous digital bit-serial design methodology to implement the algorithm in low cost ASIC form.As well as b e i g compatible with low cost standard cell design, fabrication. and test technologies, the bit-serial approach has the inherent advantage of producing extremely efficient cost effective designs.2. THE LYON COCHLEA MODEL ALGORITHM 2.1 Algorithm Topology Figure 1, (over the page) shows the block diagram of the algorithm. The frequency selective displacement characteristic of the basilar membrane is modelled using a serial connection of 71 filters. Each filter consists of a cascade connection of a second order recursive (resonance) filter and a first order section. Each node in the filter chain is tapped and fed to a half-wave-rectifier (HWR) to model the hair cell response. The hwr...
An evaluation of commercial off-the-shelf speaker verification systems is reported. The performance of several systems, which were offered for testing, is analyzed against criteria designed to identify strengths and weaknesses that would determine their suitability for the use by government service agencies. Results for three text-dependent systems by Nuance, Persay and Scansoft are presented in this paper.
This paper describes the design and implementation of a multi-channel formant speech synthesiser Application Specific Integrated Circuit (ASIC). The primary objective of this research is the development of an efficient bit-serial VLSI structure which has sufficient acoustical and processing performance for high quality and intelligibility multih n e l synthetic speech production. Functional design was performed using the Denyer/Renshaw FIRST Silicon Compiler. Also described in this paper is the approach to the implementation of a technology independent FIRST bit-serial primitive operator library using the MODEL Hardware Description Language. This library has been implemented on a European Silicon Structures (ESZ) SOLO-1000 Standard cell design tool and has been used to implement the device.
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