Although negative-bias-temperature instability in metal-oxide-semiconductor integrated circuits has been minimized empirically, the exact mechanism is unknown. We argue in this paper that the mechanism of negative-bias-temperature instability can be modeled by a first-order electrochemical reaction between hydrogenated trivalent silicon, a neutral water-related species located in the oxide near the Si-SiO2 interface, and holes at the silicon surface to form neutral trivalent silicon and a positively charged water-related species. To show that such a reaction describes the phenomenon, we show that (1) water must be present in the oxide near the Si-SiO2 interface, (2) induced interface and oxide-fixed charge densities are equal, (3) the saturation interface-trap and oxide-fixed charge densities depend on the initial hole concentration at the silicon surface or aging field, (4) the buildup of these charge densities follows first-order reaction kinetics, and (5) time constants for this charge buildup are independent of aging field. The measurements which are done to demonstrate these features combine room-temperature charge measurement using the Q-C method with current measurements during accelerated aging.
Articles you may be interested inAerial audiograms of Steller and California sea lions measured using auditory steadystate response methods.The high-low-frequency capacitance method for determining the interface trap density is widely used in studying the effects of ionizing radiation on thermally grown Si0 2 , and in verifying the trivalent silicon interface traps first discovered in electron paramagnetic resonance studies. It is shown that the high-law-frequency capacitance method gives fictitious interface trap density peaks because of the departure of the I-MHz high-frequency capacitance from the ideal high-frequency capacitance. This method gives accurate values of the interface trap density near the center of the silicon band gap, but for a given high frequency, the range of band-gap energy over which accurate values are obtained decreases with increasing interface trap density. Interface trap density is obtained over a band-gap energy range with an accuracy that is independent of interface trap density from a comparison of the measured and calculated slopes of gate bias versus equilibrium band-bending curves using the Q-C (charge-capacitance) method. The accuracy of this method is verified using the conductance method. This work shows that it is not likely that interface traps are trivalent silicon defects superimposed on a Ushaped background interface trap distribution of unknown identity.
Low pressure chemical vapor deposition of polysilicon in a lamp heated rapid thermal processor (RTCVD) has been studied. Polysilicon films were deposited using SiH4 diluted in Ar. Structural characterization of the films was accomplished by transmissionelectron microscopy (TEM), scanning tunneling microscopy (STM), secondary ion mass spectroscopy (SIMS), auger electron spectroscopy (AES) and ultraviolet surface reflectance measurements. Smooth polysilicon films were obtained at deposition temperatures above 700ºC with rms roughness values better than 100 Å. Both p- and n- polysilicon gated MOS capacitors were fabricated using 80 - 200 Å thick gate oxides grown by dry oxidation in a conventional furnace. Polysilicon doping was achieved by ion-implantation and rapid thermal annealing (RTA). Our results show that the electrical properties ofthe capacitors fabricated using RTCVD polysilicon are comparable to those of conventional polysilicon. Dopant diffusion through the gate is a problem for both types of polysilicon and can lead to a degradation of the electrical properties.
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