The design, simulation and optimization of complex continuous-time (CT) circuits like Sigma-Delta modulators require large computation times when using only transistor-level analog simulators like CADENCE Spectre or PSpice. Effective high-level system modeling should be considered in order to reduce the conception effort. However, the closed-loop architecture characteristics and technology requirements should be strictly observed on the respective models. In this work, we present a design methodology and the resulted application tools implying the extraction of CADENCE schematics for analog elements into robust macro-models for MATLAB-SIMULINK and VHDL-AMS. Upon designer's choice, the resulted macromodels can be used to implement and optimize a whole modulator in the SIMULINK object-oriented environment or the code-based analog VHDL process. Using the proposed methodology, fast simulations of a sixth-order CT Sigma-Delta modulator have been performed. I.
Novel CMOS technologies are rapidly migrating towards the nanometer world. The design and optimization of complex analog circuits implying these processes is impracticable when using only transistor-level electronic design automation (EDA) tools. Efficient design methodologies including behavioral modeling are inevitable, but the high-level models should incorporate accurate circuit characteristics and technological limitations. One solution consists in using a refined top-down design process where the macro-models are extracted from the analog block elements (e.g. amplifiers, filters) implemented on specific technologies. These fast-simulating models can be used for the high-level simulation and optimization of the entire system. We propose in this paper a complete design methodology implying the above elements and the corresponding application framework based on the interface between MATLAB and CADENCE software tools. SIMULINK and VHDL-AMS are used for the high-level system modeling. A continuous-time (CT) Sigma-Delta modulator application is presented.
The conception of analog and mixed-signal functions requires great effort because the complex analog parts should be recursively optimized based not only on system-level requirements but also on technological limitations and imperfections. High-level behavioral models used for chip-level simulations can be employed using multi-domain hardware description languages (HDL), but they are usually manually written and lack technological characteristics. Moreover, automatic resizing and optimization at the transistor level are very limited, and the behavioral models cannot be readjusted to changes at the transistor level. In this paper, we present an efficient design methodology implying the automatic optimization of cells at the transistor level using a modified Bayesian Kriging approach and the extraction of robust analog macro-models, which can be directly regenerated during the optimization process. Coherent results were obtained when using the proposed methodology for the conception of a sixthorder continuous-time (CT) Sigma-Delta () modulator. I.
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