No abstract

The increasing importance of energy e ciency has produced a m ultitude of hardware devices with various power management features. This paper investigates memory controller policies for manipulating DRAM power states in cache-based systems. We develop an analytic model that approximates the idle time of DRAM chips using an exponential distribution, and validate our model against trace-driven simulations. Our results show that, for our benchmarks, the simple policy of immediately transitioning a DRAM chip to a lower power state when it becomes idle is superior to more sophisticated policies that try to predict DRAM chip idle time.

One of the major challenges of post-PC computing is the need to reduce energy consumption, thereby extending the lifetime of the batteries that p ower these mobile devic es. Memory is a particularly important tar get for e orts to improve energy e ciency. Memory technolo gy is becoming available that o ers power management features such as the ability to put individual chips in any one of several di erent power modes. In this paper we explor e the interaction of page plac ement with static and dynamic har dware p olicies to exploit these emer ginghardwar efeatures. In p articular, we c onsider p age allo cation p olicies that c an be employed b y an informed operating system to complement the hardware power management strategies. We perform experiments using two complementary simulation envir onments: a tracedriven simulator with workload traces that are r epresentative of mobile computing and an execution-driven simulator with a detaile d processor/memory model and a more memoryintensive set of benchmarks (SPEC2000). Our r esults make a compelling case for a cooperative hardwar e/softwar e approach for exploiting power-aware memory, with down to as little as 45% of the Energy Delay for the best static policy and 1% to 20% of the Ener gy Delay for a traditional fullpower memory.

One of the major challenges of post-PC computing is the need to reduce energy consumption, thereby extending the lifetime of the batteries that p ower these mobile devic es. Memory is a particularly important tar get for e orts to improve energy e ciency. Memory technolo gy is becoming available that o ers power management features such as the ability to put individual chips in any one of several di erent power modes. In this paper we explor e the interaction of page plac ement with static and dynamic har dware p olicies to exploit these emer ginghardwar efeatures. In p articular, we c onsider p age allo cation p olicies that c an be employed b y an informed operating system to complement the hardware power management strategies. We perform experiments using two complementary simulation envir onments: a tracedriven simulator with workload traces that are r epresentative of mobile computing and an execution-driven simulator with a detaile d processor/memory model and a more memoryintensive set of benchmarks (SPEC2000). Our r esults make a compelling case for a cooperative hardwar e/softwar e approach for exploiting power-aware memory, with down to as little as 45% of the Energy Delay for the best static policy and 1% to 20% of the Ener gy Delay for a traditional fullpower memory.

One of the major challenges of post-PC computing is the need to reduce energy consumption, thereby extending the lifetime of the batteries that p ower these mobile devic es. Memory is a particularly important tar get for e orts to improve energy e ciency. Memory technolo gy is becoming available that o ers power management features such as the ability to put individual chips in any one of several di erent power modes. In this paper we explor e the interaction of page plac ement with static and dynamic har dware p olicies to exploit these emer ginghardwar efeatures. In p articular, we c onsider p age allo cation p olicies that c an be employed b y an informed operating system to complement the hardware power management strategies. We perform experiments using two complementary simulation envir onments: a tracedriven simulator with workload traces that are r epresentative of mobile computing and an execution-driven simulator with a detaile d processor/memory model and a more memoryintensive set of benchmarks (SPEC2000). Our r esults make a compelling case for a cooperative hardwar e/softwar e approach for exploiting power-aware memory, with down to as little as 45% of the Energy Delay for the best static policy and 1% to 20% of the Ener gy Delay for a traditional fullpower memory.

Phenomenal improvements in the computational performance of multiprocessors have not been matched by comparable gains in I/O system performance. This imbalance has resulted in I/O becoming a signi cant bottleneck for many scienti c applications. One key to overcoming this bottleneck is improving the performance of parallel le systems. The design of a high-performance parallel le system requires a comprehensive understanding of the expected workload. Unfortunately, u n til recently, no general workload studies of parallel le systems have been conducted. The goal of the CHARISMA project was to remedy this problem by c haracterizing the behavior of several production workloads, on di erent machines, at the level of individual reads and writes. The rst set of results from the CHARISMA project describe the workloads observed on an Intel iPSC/860 and a Thinking Machines CM-5. This paper is intended to compare and contrast these two w orkloads for an understanding of their essential similarities and di erences, isolating common trends and platform-dependent v ariances. Using this comparison, we are able to gain more insight i n to the general principles that should guide parallel le-system design.

No abstract

Energy consumption is becoming a limiting factor in the development of computer systems for a range of applica