Interfacial properties currently hinder the performance of Si/organic heterojunction solar cells for an alternative to high-efficiency and low-cost photovoltaics. Here, we present a simple and repeatable wet oxidation method for developing the surface passivation layer, SiOx, on the Si surface for the fabrication of high-efficiency Si/poly(3,4-ethylene-dioxythiophene):polystyrenesulfonate (PEDOT:PSS) heterojunction solar cells. The uniform and dense SiOx thin layer introduced by the oxidizing aqueous solution of H2O2 or HNO3 provided the better surface passivation and stronger wettability of the Si surface, compared to those in the native oxide case. These two types of progress helped create a lower defect density at the Si/PEDOT:PSS interface and thus a high-quality p-n junction with a lower interface recombination velocity. As a result, the HNO3-oxidized device displayed better performance with a power conversion efficiency (PCE) of 11%, representing a 28.96% enhancement from the PCE of 8.53% in the native oxide case. The effects on the performance of the Si/PEDOT:PSS hybrid solar cells of the wet oxidation treatment procedure, including the differences in surface roughness and wettability of the Si substrate, the quality and thickness of the SiOx, etc., were explored extensively. Such a simple and controllable oxidizing treatment could be an effective way to promote the interfacial properties that are an important cornerstone for more efficient Si/organic hybrid solar cells.
Hydrogenated nanocrystalline silicon oxide (nc‐SiOx:H) layers exhibit promising optoelectrical properties for carrier‐selective‐contacts in silicon heterojunction (SHJ) solar cells. However, achieving high conductivity while preserving crystalline silicon (c‐Si) passivation quality is technologically challenging for growing thin layers (less than 20 nm) on the intrinsic hydrogenated amorphous silicon ((i)a‐Si:H) layer. Here, we present an evaluation of different strategies to improve optoelectrical parameters of SHJ contact stacks founded on highly transparent nc‐SiOx:H layers. Using plasma‐enhanced chemical vapor deposition, we firstly investigate the evolution of optoelectrical parameters by varying the main deposition conditions to achieve layers with refractive index below 2.2 and dark conductivity above 1.00 S/cm. Afterwards, we assess the electrical properties with the application of different surface treatments before and after doped layer deposition. Noticeably, we drastically improve the dark conductivity from 0.79 to 2.03 S/cm and 0.02 to 0.07 S/cm for n‐ and p‐contact, respectively. We observe that interface treatments after (i)a‐Si:H deposition not only induce prompt nucleation of nanocrystals but also improve c‐Si passivation quality. Accordingly, we demonstrate fill factor improvement of 13.5%abs from 65.6% to 79.1% in front/back‐contacted solar cells. We achieve conversion efficiency of 21.8% and 22.0% for front and rear junction configurations, respectively. The optical effectiveness of contact stacks based on nc‐SiOx:H is demonstrated by averagely 1.5 mA/cm2 higher short‐circuit current density thus nearly 1%abs higher cell efficiency as compared with the (n)a‐Si:H.
Silicon heterojunction (SHJ) solar cells have reached high power conversion efficiency owing to their effective passivating contact structures. Improvements in the optoelectronic properties of these contacts can enable higher device efficiency, thus further consolidating the commercial potential of SHJ technology. Here we increase the efficiency of back junction SHJ solar cells with improved back contacts consisting of p-type doped nanocrystalline silicon and a transparent conductive oxide with a low sheet resistance. The electrical properties of the hole-selective contact are analysed and compared with a p-type doped amorphous silicon contact. We demonstrate improvement in the charge carrier transport and a low contact resistivity (<5 mΩ cm2). Eventually, we report a series of certified power conversion efficiencies of up to 26.81% and fill factors up to 86.59% on industry-grade silicon wafers (274 cm2, M6 size).
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