In medical imaging, the automatic diagnosis of kidney carcinoma has become more difficult because it is not easy to detect by physicians. Pre-processing is the first identification method to enhance image quality, remove noise and unwanted components from the backdrop of the kidneys image. The pre-processing method is essential and significant for the proposed algorithm. The objective of this analysis is to recognize and classify kidney disturbances with an ultrasound scan by providing a number of substantial content description parameters. The ultrasound pictures are prepared to protect the interest pixels before extracting the feature. A series of quantitative features were synthesized of each images, the principal component analysis was conducted for minimizing the number of features to produce set of wavelet-based multi-scale features. Dragonfly algorithm (DFA) was executed in this method. In the proposed work, the design and training of a random decision forest classifier and selected features are implemented. The classification of e-health information using ideal characteristics is used by the RF classifier. The proposed technique is activated in MATLAB/simulink work site and the experimental results show that the peak accuracy of the proposed technique is 95.6% using GWO-FFBN techniques compared to other existing techniques. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.
In this paper, a generic filter bank architecture for 2D FIR filter is proposed using block processing, symmetry in the filter coefficients, and memory-based multipliers. The different symmetry filters are considered as sub-filters of the filter bank to decrease the number of multipliers and the desired filter can be selected using control logic to reduce the power consumption. The block processing is incorporated to increase the throughput of the filter. Due to this block processing, memory sharing and memory reuse are achieved to optimize the architecture in terms of area, memory, and power. In each filter, the conventional multipliers are replaced with Distribute Arithmetic (DA) based memory multipliers to decrease the delay, power, and area of each sub-filter. The proposed design is coded by Verilog HDL and synthesized using Cadence Genus tools in 45 nm technology. The physical design is carried out using Cadence Innovus tools. The proposed design results are compared with state-of-the-art works.
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