we describe a new global routing algorithm designed SPeCifiCaY for sea-of-gates circuits. The algorithm has generalized to handle g: (~~t~o which seeks to even congestion, (3) a oveflows and reduces the congestion, (4) vertical track assignment, and (5) congestion evening at the detailed global routing level. ~n tests on the MCNC benchmark Circuits, the algorithm produced layouts with an average of 11% fewer routing tracks than the other algorithms. In tests on gate array benchmark circuits. the algorithm not only achieved uniform channel densities, but the maximum channel densities it produced are the lowest values that have ever been reported.types of hierarchical approaches: the topdown approach [Bur831 and the bottom-up approach [Mar84]. The basic principles behind these two different approaches are that all the ne6 are routed simultaneously at each hierarchical level, and the solutions at a hierarchical level are refined at the next hierarchical level. Hence, the problem of net-ordering is avoided. Hierarchical approaches Usually Suffer from difficulties with resolving the Seams between the set of subproblems on a given level of hierarchy. Constructive approaches have also been used in the global routing of gate arrays [Li84]. In Li's approach [Li84], based on the distribution of the pins and a congestion analysis, the global router first constructs the solutions at chip's periphery region and then proceeds inward. But this approach onlv seeks to route 100% of the nets and does not seek to minimize the total channel m e~d ,(2) a two-stage coacse global muting muting procedure which
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