AbstracI n this paper wc present the design of U Two Dimensio n a 1 11 isr w t P Cosin e Tran q o rm (2 D-D CT) y ro c e ssor und cis iniplPnieniution itsinx 0.6 [L7lL (;allium ArscJnidP Techtiol oxy. The archi ti) cturr (IJ' the processor, thut resembles uti FCT-MMM (Fust Cosine Transjbrm-Matrix Matrix Multiplicarion) urchitrcture. was dewloped using Distrihidted Ariihtnriic. (0.4) in order to redui%c the a r w riquired. Thi. proc-tjssor has uboui 50k trunsisiors und occupies an ureu of 31.8 i r ! m 3 . I t is a h k io process 400 Myixels ptjr secvnd und ut a c.lor.liJi.rir/ueticy of600 M H z , which is fat beyond thcJ rtJyuirc~nwiiis for real rim(. high d&iitiotr moving pictims in the MPE(;2 standard. Speciul cwnsideration is given to thc implrmi~niotion of' U transposition RAM which rmstitutc~s thi' horili~tieik of t h e algorithm. A 64 word x 12 bit, 1 ns access ritne Truiispositioii RAM was dewloped using U n w 1)ynarnii~ RAM c~) l l .
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