IntroductionThe swift advance of multimedia and multi-tasking computing systems greatly demands high bandwidth and multi bank DRAMS [ 11. To meet these requirements, several challenges regarding the chip size penalty and noise concems associated with multi-I/O lines should be resolved. This paper describes a 2SV, 288Mb DRAM with 32 banks architecture achieving a peak bandwidth of 2.0GB/s using both edge of 5OOMHz differential clocks and 18-I 1 0 organization. This chip features 1) an area-and performanceefficient chip architecture with well-mixed high speed interface circuits with DRAM peripheral circuits to increase cell efficiency compared to the previous work [ 11, 2) a multi-level controlled equalizing scheme and a distributed sense amplifier driving scheme to enhance DRAM core timing margin while digressing from conventional sub-wordline driving scheme, having 352 cells per sub-wordline, 3) an area-efficient column redundancy scheme with multiple fuse-boxes instead of excessive spare memory cell arrays for multi-I/O architecture, 4) a zero-dc-current receiver with a counter kick-back coupling scheme to reduce the reference coupling noise, and 5) a PVT insensitive current control scheme. Chip ArchitectureWith the trend of multi-bank and multi-YO schemes in DRAM to achieve high system performance, an area-efficient architecture is highly demanded. Three techniques are employed to enhance the cell efficiency: sharing of IO-SA and write driver between top and bottom cell arrays, merged high speed interface circuits with DRAM circuits, and adoption of 352 cell per sub-wordline driver. (SWD)Figure l(a) shows an area-efficient overall chip architecture of the 288Mb DRAM consisting of the stacked 32 banks (16 banks for each top and bottom) of 9Mb cell arrays per bank. Row decoder and repeatable RAS array circuits are located at the center of each 64Mb (72Mb) cell array mat, and column decoders and column redundancy control circuits are placed at the edge of each mat. When an active command is issued, 4.5Mb array from each of two diagonal mat pair is accessed to balance the noise environment, resulting in 2Kbyte page activation. For read or write operation, 144 VO lines from these two diagonal mat pair are connected to global pipeline and shared IO-SAIWrite-driver block which consists of just 144 YO-SAS and 144 write drivers with prefetch registers, resulting in the reduction of die area by 2.1% comparing to the architecture which assigns to each of top and bottom 16 banks its own YO circuitry. To increase cell efficiency more (2.9%) by reducing the number of sub-wordline drivers compared to the previous work [l], 352 cell per sub-wordline is implemented to optimize both chip size penalty and DRAM performance (AC timing such, as tRP, tRCD, etc.). Further reduction of chip size penalty can be achieved using mixture of DRAM peripheral circuits (random circuits for address and command input buffers and control clock generators) with the high speed interface circuits to increase the overall area efficiency by optimally p...
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