The optimum high-frequency Class-F loading conditions are inferred, accounting for the effects of actual output device behavior, and deriving useful charts for an effective design. The important role of the biasing point selection is stressed, demonstrating that it must be different from the Class-B theoretical one to get the expected improvement. The IMD behavior of the Class-F amplifier is presented and the large-signal sweet-spot origin in the IMD output characteristics is discussed, together with possible strategies to improve intermodulation distortion performances. The control of the sweet spot position is demonstrated via proper terminating impedances, both at fundamental and harmonic frequencies and low frequencies.
This paper presents a MOS-only high power supply rejection (PSRR) voltage reference with a very low temperature coefficient (TC) that consumes only tens of nano-Watt. It is composed by a threshold voltage monitor circuit with no resistors, cascaded with a thermal voltage generator, adequate for fabrication in standard processes. Since the MOS transistors operate in subthreshold and near-threshold regimes the current consumption is very low. The operation of the circuit is analytically described and a design methodology is proposed. Post-layout simulations for a design in a 130 nm CMOS process are presented, resulting a reference voltage around 670 mV with a best case TC of 1.5 ppm/ • C for the -40 to +125 • C range and an average TC of 20 ppm/ • C over process variations, untrimmed. A very low sensitivity to VDD is achieved, resulting a PSRR lower than -71 dB at 100 Hz and a line sensitivity (LS) lower than 576 ppm/V for a supply range from 1 to 3 V. The area is very small, 0.0084 mm 2 including the start-up stage.
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