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Optical clock distribution is an attractive technique to avoid clock skew in highspeed digital systems. For short lengths free space distribution by holographic optical elements (HOE) has specific advantages. We will report on the requirements of the optical system in respect of necessary light power and its equipartition to the photoreceivers. We give an estimation for the maximum number for optical fan-out considering especially ECL circuits. Specific system constraints lead to a certain layout for the whole arrangement. The realization of a distinct HOE type is carried out in form of a binary phase reflection HOE which is produced by dry etching of silicon. The measured diffraction efficiency is close to the theoretical limit.

The design and the modelling results of an 8 channel parallel optical chip to chip interconnection consisting of a laser diode (LD) array, a single-mode waveguide (WG) array, and a photodiode (PD) array with 8 channels each are presented. The separation of the channels is 125 im, so the overall width of the 8 channel line is only I mm. The electronic and the optoelectronic components will be mounted on a silicon substrate wafer and the waveguides on a second silicon wafer which will be fixed upside down on the substrate. The LDs are envisaged to be AlGaAs singlequantum well types though the first implementation will be realized with conventional A1GaAs MCRW semiconductor lasers with a wavelength of 0.85 rim. The PDs are fabricated in standard silicon technology, the silica WGs with the flame hydrolysis technique and reactive ion etching. The trade off between large fabrication tolerances and the desired high coupling efficiencies is discussed. Mounting techniques for the LD-and PD-arrays are presented. A comparison between this optical interconnection and an equivalent electrical one is given.

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