The Timepix3, hybrid pixel detector (HPD) readout chip, a successor to the Timepix [1] chip, can record time-of-arrival (ToA) and time-over-threshold (ToT) simultaneously in each pixel. ToA information is recorded in a 14-bit register at 40 MHz and can be refined by a further 4 bits with a nominal resolution of 1.5625 ns (640 MHz). ToT is recorded in a 10-bit overflow controlled counter at 40 MHz. Pixels can be programmed to record 14 bits of integral ToT and 10 bits of event counting, both at 40 MHz. The chip is designed in 130 nm CMOS and contains 256 × 256 pixel channels (55 × 55 µm 2 ). The chip, which has more than 170 M transistors, has been conceived as a general-purpose readout chip for HPDs used in a wide range of applications. Common requirements of these applications are operation without a trigger signal, and sparse readout where only pixels containing event information are read out.A new architecture has been designed for sparse readout and can achieve a throughput of up to 40 Mhits/s/cm 2 . The flexible architecture offers readout schemes ranging from serial (one link) readout (40 Mbps) to faster parallel (up to 8 links) readout of 5.12 Gbps. In the ToA/ToT operation

We examine two digital architectures for front end pixel readout chips, Velopix and Timepix3. These readout chips are developed for tracking detectors in future high energy physics experiments. They must incorporate local intelligence in pixels for time-over-threshold measurement and sparse readout. In addition, Velopix must be immune to single-event upsets in its digital logic. The most important requirements for both chips are pixel size, timing resolution, low power and high-speed sparse readout. We describe the transaction level architectural models of the chips using SystemVerilog. The correctness of the models is ensured using Open Verification Methodology. We will also discuss the advantages gained from transaction level modeling.

In this paper, two digital column architectures suitable for sparse readout of data from a pixel matrix in trigger-less applications are presented. Each architecture reads out a pixel matrix of 256 x 256 pixels with a pixel pitch of 55 μm. The first architecture has been implemented in the Timepix3 chip, and this is presented together with initial measurements. Simulation results and measured data are compared. The second architecture has been designed for Velopix, a readout chip planned for the LHCb VELO upgrade. Unlike Timepix3, this has to be tolerant to radiation-induced single-event effects. Results from post-layout simulations are shown with the circuit architectures.

Due to many favorable properties it is very attractive to use Micro Pattern Gas Detectors (MPGDs) as gas amplification stages in Time Projection Chambers (TPCs). Especially the high granularity, intrinsic suppression of ion backflow, high rate capability and almost no distortions due to E × B effects are desirable in future particle physics detectors. To fully exploit the potential of combining MPGDs and TPCs the pad size in the readout plane should be adapted to the structure size of the gas amplification stage. The Timepix chip is well suited for the use as readout chip in gaseous detector by providing metalized pads to pick up the charge.We have constructed a test chamber with a triple GEM and Timepix readout and a maximum drift distance of 26 cm. With this setup we have studied the performance of the detector in various operation environments. Different setups for tests with cosmic rays and for tests in high magnetic fields have been realized. In these environments key detector parameters such as spatial resolution have been studied in dependence on different gas mixtures. We have seen strong evidence for observation of individual electrons and a spatial resolution of down to 80 µm has been measured.

GOSSIPO-3 is a demonstrator of a front-end chip designed in IBM 130 nm CMOS in collaboration between Nikhef (Amsterdam) and the Physics Department of the University of Bonn for the read-out of Micro-Pattern Gas Detectors. The prototype features charge sensitive amplifiers, discriminators, a high resolution Time to Digital Converter (TDC), two different Low Drop Out (LDO) voltage regulators for supply voltage control of the Time to Digital Converter, biasing circuits and control logic on a 2 × 1 mm2 die. The chip can be operated in a time measuring mode or an event counting mode. Following the prototype announcement at the TWEPP 2009, measurement data on gain, noise performance, channel to channel ToT spread and LDO load step responses is now available. The measurement results confirm the high gain and low noise (ENC = 25 e−) predicted by simulations. Stable and reproducible time bin sizes of the TDC are also confirmed.