In integrated circuit manufacturing with multi-level interconnect, it is important to have a planar surface preceding the next layer to avoid topography-induced patteming failure. Historically, Chemical-Mechanical Polishing (CMP) dramatically improved the planarity of inter-metal dielectrics. It is well known that CMP causes dishing in the planarized layer with non-uniform distribution of active structures, thus creating significant topography challenges for subsequent patteming. One solution for this dishing phenomenon is introduction of pattem fill with dummy structures as a method to improve planarity for a given layer. However, dummy pattem fill adds capacitive load and thus, parasitic effects on both analog and digital circuits.Evaluation of the effects for several strategies of metal pattem fill is undertaken in this work to understand the optimization of planarity and parasitic capacitance. The location height of hundreds of points within a field or even across a wafer is measured using the wafer flatness metrology scan available on an ASML stepper. Figures 1 and 2 display wafer level topography maps with Figure 1 illustrating the planarity of a circuit without pattern fill. Figure 2 shows the same circuit with metal dummy pattern fill and significant topographical improvement over Figure 1. Figure 3 demonstrates the topography analysis on a 1x2 die field o f a different circuit.Multiple fill strategiesincluding shapes and spacings -are examined in this work for topographical and parasitic performance.Initial parasitic capacitance analysis is performed by closed form solution. Figure 4 shows the structural schematic'of the fill-loaded system in the worst case where all fill features are at minimum space alongside and undemeath a key signal line for a given technology. Figure 5 displays the equivalent circuit of this system (with the C3/CS branch doubled in the calculation).Using this basic construct and varying the key features, the worst-case conditions are calculated and the results graphed in Figure 6. One can see the interesting effect of improved planarity on capacitive loading where, as one moves the fill away from features the capacitance of an unfilled circuit is worse than a filled circuit due to the thinning of the inter-metal dielectric. In first order, this shows the importance ofplanarity on capacitive load, but the results are overly generous in assuming that the filled circuit is equally planar regardless of fill density. Improvements to this first order calculation are required to find the tradeoff point and are in progress.Based on these calculations, guideline rules are defined for fill size, shape, and proximity. Once the fill strategy is devised, the layout data is prepared for each approach. Finally, using the analysis of a circuit-level parasitic capacitance tool, the estimated effect on various circuit nets is calculated, which are graphically presented as in Figure 7. In this figure, the capacitance of each net prior to fill is plotted on the x-axis and the post-fill capacitance on ...
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