Computer architecture is an important subject for informatics and electrical engineering courses, where students get to know how a CPU works internally. However, the students exhibit some difficulties in this subject. This is due to the lack of versatile educational tools that simulate the operation of a processor in an intuitive, integrated, graphical and configurable way.One of the most used processor architectures for teaching computer architecture is MIPS. The architecture has a few different versions, but the most used for teaching are the unicycle and the 5-stage pipeline.In this dissertation, an educational MIPS simulator, DrMIPS, is described. This tool simulates the execution of an assembly program on the CPU, step-by-step, and displays the status of the datapath graphically. Registers, data memory and assembled code are also displayed, and a "performance mode" for latencies and critical path analysis is also provided. Both unicycle and pipeline implementations are supported and the CPUs and their instruction sets are configurable. The pipeline implementation includes complete hazard detection and resolution.The tool seeks to help students to understand topics like the composition and operation of a datapath, pipelining, instruction encoding and processor measuring. It is available not only for PCs but also for Android tablets. None of the other existing tools have a version for Android and this is a platform that is becoming very popular. The tool supports multiple languages and is fairly intuitive and versatile on both platforms.i ii ResumoA arquitectura de computadores é uma disciplina importante dos cursos de engenharia informática e electrotécnica, onde os estudantes ficam a conhecer como um CPU funciona internamente. No entanto, os estudantes demonstram algumas dificuldades nesta disciplina. Isto deve-se à ausência de ferramentas educativas versáteis que simulem o funcionamento de um processador de forma intuitiva, integrada, gráfica e configurável.Uma das arquitecturas de processadores mais usadas para o ensino de arquitectura de computadores é o MIPS. A arquitectura tem algumas versões diferentes, mas as mais usadas no ensino são as versões uniciclo e pipeline de 5 etapas.Nesta dissertação, um simulador educativo do MIPS, DrMIPS, é descrito. Esta ferramenta simula a execução de um programa em assembly no CPU, passo-a-passo, e mostra o estado do caminho de dados graficamente. Registos, memória de dados e código assemblado também são mostrados, e um "modo de desempenho" para análise de latências e caminho crítico é fornecido. Ambas as implementações uniciclo e pipeline são suportadas e os CPUs e seus conjuntos de instruções são configuráveis. A implementação pipeline inclui detecção e resolução completa de conflitos.A ferramenta pretende ajudar os estudantes a entender tópicos como a composição e funcionamento de um caminho de dados, pipelining, codificação de instruções e desempenho de processadores. Está disponível não só para PCs mas também para tablets Android. Nenhuma das outras ferra...
As the industry progresses, power quality problems become more and more relevant. The increase of non-linear loads in industries, leads to higher current harmonic distortion and low power factor. In order to mitigate these problems, this paper validates a shunt active power filter (SAPF). The adopted topology and its control algorithm are analyzed through computer simulations considering real industrial load models, which were elaborated from data collected in power quality analyzers that were connected to different points of an industry. The results achieved validate the correct operation of the applied SAPF, as well as it presents the improvements obtained of the total current distortion and neutral current.
This paper presents a study on the parallel association of power semiconductors. The main purpose of this paper is to demonstrate that the parallel association of lower rated power semiconductors can be more advantageous than the use of a single higher rated power semiconductor, both economically and in terms of dynamic performance, i.e., switching behavior and semiconductor temperature. In this context, two different power semiconductor technologies were tested: (1) Insulated gate bipolar transistors (IGBTs); and (2) Metal oxide semiconductor field effect transistors (MOSFETs). For each technology, the adopted methodology consisted of verifying the dynamic performance of a single higher rated power semiconductor, comparing it with the dynamic performance of a set of five parallel-connected lower rated power semiconductors, focusing on the current sharing between the devices. The obtained experimental results demonstrate that the parallel connection of lower rated power semiconductors can be advantageous over the use of a single higher rated power semiconductor above certain power levels, offering better switching characteristics and lower cost.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.