Solution‐printed organic single‐crystalline films hold great potential for achieving low‐cost manufacturing of large‐area and flexible electronics. For practical applications, organic field‐effect transistor arrays must exhibit high performance and small device‐to‐device variation. However, scalable fabrication of highly aligned organic crystalline arrays is rather difficult due to the lack of control over the crystallographic orientation, crystal uniformity, and thickness. Here, a facile solution‐printing method to fabricate centimeter‐sized highly aligned organic crystalline arrays with a thickness of a few molecular layers is reported. In this study, the solution shearing technique is used to produce large‐area, organic highly crystalline thin films. Water‐soluble ink is printed on the hydrophobic surface of organic crystalline films, to selectively protect it, followed by etching. It is shown that the addition of a surfactant dramatically changes the fluid drying dynamics and increases the contact line friction of the aqueous solution to the underlying nonwetting organic crystalline film. As a result, centimeter‐scale highly aligned organic crystalline arrays are successfully prepared on different substrates. The devices based on organic crystalline arrays show good performance and uniformity. This study demonstrates that solution printing is close to industrial application and also expands its applicability to various printed flexible electronics.

2D organic semiconductor crystals (2DOSCs) have extraordinary charge transport capability, adjustable photoelectric properties, and superior flexibility, and have stimulated continuous research interest for next‐generation electronic and optoelectronic applications. The prerequisite for achieving large‐area and high‐throughput optoelectronic device integration is to fabricate high‐resolution 2DOSC arrays. Patterned substrate‐ and template‐assisted self‐assembly is an effective strategy to fabricate OSC arrays. However, the film thickness is difficult to control due to the complicated crystallization process during solvent evaporation. Therefore, the manufacturing of 2DOSC arrays with high‐resolution and controllable molecular‐layer numbers through solution‐based patterning methods remains a challenge. Herein, a two‐step strategy to produce high‐resolution layer‐controlled 2DOSC arrays is reported. First, large‐scale 2DOSCs with well‐defined layer numbers are obtained by a solution‐processed organic semiconductor crystal engineering method. Next, the high‐resolution layer‐controlled 2DOSC arrays are fabricated by a polydimethylsiloxane mold‐assisted selective contact evaporation printing technique. The organic field‐effect transistors (OFETs) based on 2DOSC arrays have high electrical performance and excellent uniformity. The 2,6‐bis(4‐hexylphenyl)anthracene 2DOSC arrays‐based OFETs have a small variation of 12.5% in mobility. This strategy can be applied to various organic semiconductors and pattern arrays. These demonstrations will offer more opportunities for 2DOSCs for integrated optoelectronic devices.

Electrohydrodynamic inkjet (E-jet) printing is a promising technology to fabricate high-performance organic electronic devices due to its high resolution, low-cost and drop-on-demand characteristic. Here, we fabricate top-contact OFETs by using...

Large‐scale growth of highly crystalline single layer 2D polymers (SL‐2DPs) and their subsequent integration into memristors is key to advancing the development of high‐density data storage devices. However, leakage problems resulting from the porous structure of 2DPs continue to make such advances extremely challenging. Herein, we overcome this issue by incorporating long alkoxy chains into key molecular building blocks to obtain a highly crystalline 2DP, as visualized by scanning tunneling microscopy, and prevent metal permeation in the subsequent device fabrication process. SL‐2DP memristors constructed via direct evaporation of the top electrodes exhibit low variability (σVset = 0.14) due to the single‐monomer‐thick feature together with the high regular structure and coordination ability which minimizes the stochastic spatial distribution of conductive filaments (CFs) in both vertical and lateral dimensions. The variability is further decreased to 0.04 by confining the formation and fracture of CFs to the interface through the utilization of bilayer junctions. Using peak force tunneling atomic force microscopy, the nanometer scalability (< 50 nm2) and low power consumption of these molecular memristor devices are demonstrated.

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Flexible integrated circuits (ICs) have gained a lot of attentions in recent years for their emerging application in wearable electronics. Flexible thin-film transistors (TFTs) with low-cost and high-performance are highly desirable as essential and fundamental element for most of the flexible applications. In this paper, we fabricated single-crystalline silicon nanomembrane (SiNM) based TFTs with anodized aluminum oxide (AAO) as dielectric material on glass and flexible plastic substrates. Good quality AAO was obtained on plastic substrates at room temperature. AFM was used for surface morphology of AAO gate dielectric layers on different substrates (i.e. glass, polyethylene terephthalate (PET) and SU-8 coated PET). The electrical characteristics of the AAO gate dielectric layers on different substrates were also analyzed with metal- dielectric-metal (MIM) capacitors. SiNMs were processed with complementary metal oxide semiconductor (CMOS) compatible semiconductor process (e.g. photolithography, ion implantation, thermal annealing, reactive ion etching, metal evaporation, etc.), and then transferred to the substrates with AAO/aluminum stack layers. Performances of transistors on glass and plastic substrates were characterized. Compared with the TFT fabricated on glass substrate, TFT fabricated directly on a PET substrate have lower performance due to poor surface roughness. For optimization of the surface roughness, PET was modified with coating SU-8 photoresist. By this way, TFT had properties close to that on glass substrate. AAO that can be manufactured at room temperature provides a simple and low-cost solution for high-performance flexible single-crystalline SiNM TFTs.

Flexible thin-film transistors (TFTs) play an important role in flexible integrated circuits (ICs). Hybrid integrated transistors are highly desirable because of their high performance and simplified process. However, TFTs with a hybrid integrated heterostructure of single-crystalline semiconductor/organic dielectric layers have not yet been discussed. In this work, a flexible hybrid TFT comprised of a single-crystalline silicon nanomembrane (SiNM) semiconductor and polystyrene (PS) gate dielectric was fabricated on a PET substrate. The surface morphology of the PS dielectric layer on the PET substrate was characterized by scanning electron microscopy (SEM) and atomic force microscopy (AFM). The electrical characteristics of the dielectric layer (PS) were also analyzed. SiNM was processed with a complementary metal–oxide–semiconductor (CMOS)-compatible process and subsequently transferred to the PET substrate with a PS/ITO stacked layer to complete the assembly of the flexible hybrid SiNM/PS TFT. The electrical properties of the flexible hybrid TFT were characterized under different bending conditions (i.e., flat and bending radii of 21, 38.5, and 77.5 mm). Furthermore, the stress analysis of TFTs influenced by a variation of the dielectric materials (i.e., PS, SiO2, and Al2O3), the adhesion conditions of the SiNM/PS interface, and the dielectric thickness were also discussed. The results revealed the potential of combining an organic polymeric dielectric with inorganic single-crystalline nanomembranes to fabricate high-performance flexible hybrid TFTs.