Wrinkle-free reduced graphene oxide (rGO)/TiO(2) hybrid multilayer films were directly fabricated using an rGO solution stabilized by a TiO(2) precursor sol applied over a large area by an air spraying method without the use of additional reduction processes. In-situ insertion of the TiO(2) layer between rGO sheets dramatically increased the conductivity and carrier mobility despite the insulating properties of amorphous TiO(2). The TiO(2) situated between rGO sheets also induced significant hole doping. Electrical hysteresis caused by adsorbed water molecules and residual oxidative moieties in the rGO nanosheets vanished due to TiO(2)-assisted screening of charged impurities. These effects decreased the thermal carrier activation energy and increased the density of states at the Fermi level. Ambipolar transport properties were converted into unipolar-like hole transport characteristics by extensive hole doping in the TiO(2) layer.

CXCL12-CXCR4 signalling is essential for the correct patterning of aortic arches and pulmonary arteries during development. Superfluous arteries in Cxcl12-null lungs and the aortic arch infer a role of CXCL12 in protecting arteries from uncontrolled sprouting during development of the arterial system.

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In this paper, we present a capacitorless one-transistor dynamic random access memory (1T-DRAM) based on a double-gate GaAs junctionless transistor (JLT). The proposed 1T-DRAM exhibits an excellent reading operation with a large sensing margin between the “1” and “0” states because the excess hole charges effectively screen the electric field formed by the gate2 voltage (VGS2). In order to reduce the electric field in the drain–gate interface involved in recombination, HfO2 is used as the spacer dielectric. The 1T-DRAM obtains a long retention time of 71 ms due to a low recombination rate. Moreover, we investigate the effect of geometric parameters on DRAM characteristics. The gate length (LG) and body thickness (Tbody) have a major impact on the sensing margin and retention time. The 1T-DRAM with a long LG and a thin Tbody can operate with a low power (LP) consumption, a long retention time, and high-density integration.