We use scanning photocurrent microscopy (SPCM) to investigate the properties of internal p-n junctions as well as local defects in ambipolar carbon nanotube (CNT) transistors. Our SPCM images show strong signals near metal contacts whose polarity and positions change depending on the gate bias. SPCM images analyzed in conjunction with the overall conductance also indicate the existence and gate-dependent evolution of internal p-n junctions near contacts in the n-type operation regime. To determine the p-n junction position and the depletion width with a nanometer scale resolution, a Gaussian fit was used. We also measure the electric potential profile of CNT devices at different gate biases, which shows that both local defects and induced electric fields can be imaged using the SPCM technique. Our experiment clearly demonstrates that SPCM is a valuable tool for imaging and optimizing electrical and optoelectronic properties of CNT based devices.In semiconducting nanostructures, including carbon nanotubes (CNTs) 1, 2 and nanowires (NWs), 3 the electronic properties at various interfaces, especially metal contacts, play a crucial role, often dominating the overall performance of nanostructure-based devices. [4][5][6][7] In addition, the presence and properties of defects can cause various abnormalities in the conductance properties. To fully understand the overall conductance behavior of a nanostructure with high spatial resolution, various scanning probe microscopy (SPM) techniques have been utilized to locally perturb or electrically contact the target structures. 7,8 More recently, scanning photocurrent microscopy (SPCM) has been successfully applied to study electrical and photoelectric properties of a number of linear nanostructures, including carbon nanotubes 9, 10 and semiconducting nanowires. 11,12 The information generated by SPCM includes the band structure near nanostructure/metal interfaces, 12 carrier relaxation dynamics, 13 and detection of local defects. 10 In this paper, we report SPCM measurements of CNT transistors at different gate biases (V G 's) to investigate the electronic band structure. Our measurements reveal that the peak photocurrent (PC) spots near the metal contacts move with gate bias in the n-type regime. We measure with nanoscale resolution the intensity and polarity of these PC spots in conjunction with DC conductance to investigate the dynamics of the internal p-n junctions. We also study the effect of various local potential variations such as naturally existing defects and induced electrical field due to a partial suspension of the CNTs.Our CNT transistors were fabricated using standard photo-and electron beam lithography techniques with CVD-grown semiconducting CNTs. CNTs were first synthesized directly on a 220 nm thick thermal oxide layer on a conducting Si substrate that is also used as a back gate. Metal evaporation and liftoff were used to define drain and source electrodes. We used either Cr/Au (5/45 nm) or Ti (50 nm) for the electrodes.Our SPCM setup uses a diffraction-...
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