In order to take the advantages of the replacement gate process, improve the control of SCE, and enhance the performance of CMOSFETs, a novel method of self-aligned super-steepretrograded halo (3SRH) implantation is designed and presented in this paper. With process and device simulations, it's demonstrated that 3SRH can be used to enhance MOSFET performance. IntroductionWith aggressively scaling MOSFET gate length, the control of short-channeleffect (SCE) of the MOSFET becomes more and more difficult. Halo implantations are usually used to improve SCE. The shorter gate length, the heavier halo dose is needed. However, the heavy halo dose or high halo dopant concentration reduces channel carrier mobility, increases extension resistance, and then causes large degradation of MOSFET performance.Recently, CMOSFETs with replacement gate have been implemented in the state of the art HKMG (high-K metal gate) 32nm technology node [1]. In order to take the advantages of the replacement gate process, improve the control of SCE, and enhance the performance of CMOSFETs, a novel method of self-aligned super-steep-retrograded halo (3SRH) implantation is designed and presented in this paper. Process and device simulations are conducted to demonstrate the benefits of device performance and scaling due to 3SRH.
Effects of dopant distribution in substrate/back-gate on performance and Vt roll-off of ET-SOI MOSFETs with UT-BOX (ES-UB-MOSFETs) are simulated and studied. Lateral non-uniform dopant distributions (LNDD) in substrate, for the first time, are used to enhance scaling capability and improve Vt controllability for ES-UB-MOSFETs. Process and device simulations are conducted to demonstrate the importance of substrate dopant engineering and to search the optimization design conditions for ES-UB-MOSFETs. Fixing long channel Vt at 0.3V for both bulk MOSFETs and ES-UB-MOSFETs, ES-UB-MOSFETs with LNDD can improve Ieff@Ioff= 1e-7A/μm by 20% for nMOS and 18% for pMOS. With fixing long channel Vt at 0.3V for ES-UB-MOSFETs, LNDD enables gate length to be scaled to 20nm for both nMOS and pMOS, which is ~ 43% smaller than that of the ES-UB-MOSFETs with lateral uniform doping in substrate. A novel process flow to form LNDD is proposed and simulated.
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