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Because of the von Neumann bottleneck, neuromorphic networks aimed at in-memory computing, such as brains, are extensively studied. As artificial synapses are essential in neuromorphic networks, a photonic synapse based on slot-ridge waveguides with nonvolatile phase-change materials (PCMs) was proposed and demonstrated in an SOI platform with standard complementary metal-oxide-semiconductor (CMOS) process for a larger weight dynamic range. The change of the optical transmission spectrum of our photonic synapses was about 3.5dB higher than that of primitive synapses, which meant large weight dynamic range and more weight values. A 90.7% recognition accuracy based on our photonic synapses, which was 2.6% higher than that of primitive synapses, was realized for the MNIST handwritten digits recognition task performed by a three-layer perceptron. Besides, because of the nonvolatile nature of PCMs, the weights achieved by our photonic synapses can be stored in situ ensuring a lower consumption in in-memory computing. This framework can potentially achieve a more efficient in-memory computing neuromorphic network in silicon photonics.

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A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS technology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capacitance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resistance is 50 Ω, and the average input noise current spectral density is 9.7 pA/√Hz. Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.

In this work, a bidirectional grating coupler for perfectly vertical coupling is proposed. The coupling efficiency is enhanced using a silicon nitride (Si3N4) layer above a uniform grating. In the presence of Si3N4 layer, the back-reflected optical power into the fiber is diminished and coupling into the waveguide is increased. Genetic algorithm (GA) is used to optimize the grating and Si3N4 layer simultaneously. The optimal design obtained from GA shows that the average in-plane coupling efficiency is enhanced from about 57.5% (−2.5 dB) to 68.5% (−1.65 dB), meanwhile the average back-reflection in the C band is reduced from 17.6% (−7.5 dB) to 7.4% (−11.3 dB). With the help of a backside metal mirror, the average coupling efficiency and peak coupling efficiency are further increased to 87% (−0.6 dB) and 89.4% (−0.49 dB). The minimum feature size of the designed device is 266 nm, which makes our design easy to fabricate through 193 nm deep-UV lithography and lowers the fabrication cost. In addition, the coupler proposed here shows a wide-band character with a 1-dB bandwidth of 64 nm and 3-dB bandwidth of 96 nm. Such a grating coupler design can provide an efficient and cost-effective solution for vertical fiber-to-chip optical coupling of a Wavelength Division Multiplexing (WDM) application.