Memristor-aided logic (MAGIC) is a technique for performing in-memory computing using memristive devices. The design of a MAGIC NOR gate has been described in detail, and it serves as the basic building block for several processing-in-memory architectures. However, the input stability of the MAGIC NOR gate forces a limitation on the threshold voltages: the magnitude of the set voltage must be higher than the magnitude of the reset voltage. Unfortunately, many of the current leading resistive switching technologies, particularly, valence change memory (VCM), have the opposite ratio between the threshold voltages. In this article, we experimentally demonstrate the undesirable effects of input instability. Furthermore, we introduce three new MAGIC gates for devices with low set-to-reset voltage ratios and experimentally demonstrate their robust operation using Pt/Ta 2 O 5 /W/Pt devices. The three gates, combined with constant values, are functionally complete and are demonstrated as building blocks for in-memory logic on VCM devices. Index Terms-Logic-in-memory, memristor, memristoraided logic (MAGIC), processing-in-memory (PIM), valence change memory (VCM). I. INTRODUCTION M EMRISTIVE devices have attracted much attention, in the context of both future nonvolatile memories, as well as computation-in-memory [1]-[4]. For binary storage and computing using memristive devices, the logical states are Manuscript
A non-volatile resistive switching device is demonstrated, utilizing a 2D electron gas (2DEG) between a SrTiO3 substrate and an amorphous Al2O3 layer. A large resistance window is observed, and its origin is discussed. We pinpoint the role of the oxide interface in enabling the resistive switching behavior. The switching mechanism is proposed to be of filamentary type that is formed inside the Al2O3 layer, the result of oxygen vacancies that are driven from the interface into the insulating Al2O3 under high electric fields. These results highlight the concept of memristive devices where the 2DEG serves both as the back electrode and as the source of defects necessary for resistive switching, providing a simple and scalable process for future devices.
Modern computers suffer from a limited data transfer rate between the memory and the processing units. One of the attractive potential solutions to overcome this bottleneck is to combine processing and memory by performing computing in the same location where the data is stored. Processing-in-memory (PIM) has been demonstrated by memristor-aided logic (MAGIC) operations using resistive random access memory (RRAM) memristive devices within crossbar arrays. Nevertheless, RRAM devices are relatively slow and suffer from limited endurance. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) is another memristive technology, which is faster and has practically unlimited endurance and is therefore considered to be an attractive technology for cache-level memories. In this paper, we demonstrate MAGIC operations within an STT-MRAM array by supplying voltages suitable to achieve the current required for MRAM device switching. The proposed circuit was evaluated in SPICE simulations with the GlobalFoundries 22nm CMOS-MRAM process, including Monte Carlo simulations to verify the proposed design in the presence of process variation and device mismatch. The circuit showed more than 90% chance of functioning for the {1 1} and {0 0} input cases while it was about 85% correct for the {0 1} case.
—Modern computers suffer from a limited data transfer rate between the memory and the processing units. One of the attractive potential solutions to overcome this bottleneck is to combine processing and memory by performing computing in the same location where the data is stored. Processing-in-memory (PIM) has been demonstrated by memristor-aided logic (MAGIC) operations using resistive random access memory (RRAM) memristive devices within crossbar arrays. Nevertheless, RRAM devices are relatively slow and suffer from limited endurance. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) is another memristive technology, which is faster and has practically unlimited endurance and is therefore considered to be an attractive technology for cache-level memories. In this paper, we demonstrate MAGIC operations within an STT-MRAM array by supplying voltages suitable to achieve the current required for MRAM device switching. The proposed circuit was evaluated in SPICE simulations with the GlobalFoundries 22nm CMOS-MRAM process, including Monte Carlo simulations to verify the proposed design in the presence of process variation and device mismatch. The circuit showed more than 90% chance of functioning for the {1 1} and {0 0} input cases while it was about 85% correct for the {0 1} case.
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